Etch Stop Layer Layout for Mixed-Critical-Dimension HARC Etching
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Solution Overview
Problem
Conventional 3D NAND fabrication methods face challenges in achieving precise etching of features with different critical dimensions and etch rates, leading to over-etching or under-etching, which can damage underlying layers and impact the dimensional accuracy of semiconductor devices.
Innovation Solution
A method utilizing multiple etch stop layers in a cyclic etch process to selectively etch features with different etch rates, ensuring that faster etching features stop at the etch stop layer without damaging underlying structures, and incorporating these layers as part of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional non-selective etch processes with multiple discrete etch steps are used, then features with different critical dimensions can be etched, but the process complexity increases and manufacturing precision deteriorates due to over-etching or under-etching
Solution Approach 1:
The patent divides the layer stack into multiple segments by inserting etch stop layers between alternating oxide and nitride layers. This segmentation allows the etch process to be controlled in discrete stages, where each etch stop layer acts as a boundary that prevents over-etching into underlying layers. The etch stop layers are strategically positioned at different depths to accommodate features with different critical dimensions, enabling precise control of etching depth for each feature type without requiring multiple discrete etch steps.
Solution Approach 2:
The etch stop layers serve as intermediary elements between the oxide and nitride layers. These intermediary layers have specific etch selectivity properties that allow them to be etched at different rates compared to the surrounding oxide and nitride layers. This intermediary function enables the etch process to selectively remove material at controlled rates, preventing both over-etching and under-etching while simplifying the overall fabrication process by allowing single-step etching of multiple feature types.
2Manufacturing precision
If multiple discrete etch steps are used to etch features of different critical dimensions, then etching precision can be maintained, but the number of fabrication steps increases reducing productivity
Solution Approach 1:
The patent merges multiple discrete etch steps into a single integrated etch process by incorporating etch stop layers throughout the layer stack. The etch stop layers are designed with specific etch selectivity ratios that allow different feature types (contact holes, vias, trenches) to be etched to their respective depths within the same etch step. This merging eliminates the need for multiple sequential etch steps while maintaining dimensional accuracy, thereby improving fabrication efficiency and productivity.
Solution Approach 2:
The patent utilizes parameter changes in etch selectivity by selecting materials for etch stop layers that exhibit different etch rates compared to oxide and nitride layers. By controlling the etch selectivity parameters (through material selection and process conditions), the patent enables a single etch process to automatically terminate at different depths for different feature types based on their respective etch stop layers, maintaining dimensional accuracy while improving productivity.
3Quantity of substance
If aggressive scaling of planar structures is used to increase memory density, then storage capacity increases, but cell-to-cell interference and data retention deteriorate
Solution Approach 1:
The patent transitions from 2D planar structures to 3D vertically stacked structures, adding the vertical dimension to increase memory density. The layer stack consists of multiple alternating oxide and nitride layers stacked vertically, with etch stop layers positioned at specific depths. This vertical stacking allows for increased storage capacity while maintaining cell isolation through the etch stop layers, preventing cell-to-cell interference and preserving data retention characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances precision and efficiency in etching semiconductor devices by minimizing over-etching, maintaining structural integrity, and reducing the number of fabrication steps.
Implementation Method 1
a cyclic etch process to expose an underlayer, each cycle of the cyclic etch process including a first etch step to etch through the alternating oxide and nitride layers
Implementation Method 2
ensuring that faster etching features stop at the etch stop layer without damaging underlying structures
Data Source
AI summary
A method of forming a device includes receiving, in a processing chamber, a substrate having a layer stack comprising an etch stop layer, a stack of alternating oxide and nitride layers, and a patterned hard mask layer, the patterned hard mask layer comprising a pattern for forming a first features and a second features in the layer stack, the first features having a different geometric characteristic than the second features. And the method further includes performing, in the processing chamber, a cyclic etch process to expose an underlayer, each cycle of the cyclic etch process including a first etch step to etch through the alternating oxide and nitride layers, and a second etch step to etch through the etch stop layer.