Etch Stop Layer for Interconnect Misalignment
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Solution Overview
Problem
In the semiconductor industry, via-wire misalignment due to lithography overlay errors leads to IC defects such as accidental bridging and reliability issues like electron migration and time-dependent dielectric breakdown, as traditional multilayer interconnect structures lack an etch stop layer to prevent excessive etching of the underlying dielectric layer.
Innovation Solution
A multilayer interconnect structure is developed with an etch stop layer having a higher density and slower etching rate than the dielectric layers, which is deposited over the conductive lines to limit lateral and vertical etching, preventing misalignment-induced defects and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If lithography overlay errors occur during via formation, then via-wire misalignment happens, but this leads to bridging defects and reliability issues due to excessive etching of the underlying dielectric layer
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the conductive line and the underlying dielectric layer. This intermediate layer has a slower etching rate than the dielectric layer, acting as a buffer that prevents excessive etching from reaching the conductive line even when via alignment is poor due to lithography overlay errors.
Solution Approach 2:
The etch stop layer is deposited beforehand over the conductive line to provide protective cushioning. This pre-positioned layer compensates for potential alignment errors by absorbing the excess etching that would otherwise directly expose the conductive line, thereby preventing bridging defects and reliability issues before they occur.
2Device complexity
If no etch stop layer is present, then the fabrication process is simpler, but lateral and vertical etching of the dielectric layer becomes excessive causing via-wire misalignment defects
Solution Approach 1:
The etch stop layer serves as a mediating layer between the via etching process and the conductive line. It provides a controlled etching interface that limits lateral and vertical etching extent, ensuring precise via-wire alignment is maintained even when the overall structure complexity increases due to the additional layer.
Data Source
AI summary
A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.