Memory Array Via Formation Using Multi-Material Etch-Stop Islands

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Solution Overview

Problem

Current methods for forming memory arrays, particularly in NAND architecture, face challenges in efficiently creating conductive vias and memory cells with precise electrical coupling and structural integrity, which can lead to issues in data retention and access times.

Innovation Solution

The method involves forming islands with etch-stop materials of different compositions, allowing for the creation of through-array vias and memory cells with precise electrical coupling by etching through these islands to connect conductor tiers, thereby ensuring reliable data storage and access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to form conductive vias in NAND architecture, then manufacturing simplicity is maintained, but manufacturing precision and structural integrity deteriorate

Engineering Contradiction:

Improveconductive via formation precisionVSAvoidmanufacturing process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The conductive via formation process is segmented into multiple distinct steps: forming openings through the insulating layer, depositing conductive material, and planarizing the surface. This segmentation allows each step to be optimized independently, improving precision while managing complexity through systematic process breakdown

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary actions by pre-forming the insulating layer with embedded conductive plugs before via formation, and using planarization techniques to prepare uniform surfaces for subsequent processing. These preliminary steps ensure precise via alignment and formation while maintaining overall process manageability

Inventive Principle:

Principle #10Preliminary action

2Reliability

If memory cells are formed without precise electrical coupling, then manufacturing complexity is reduced, but data retention and access performance deteriorate

Engineering Contradiction:

Improvedata retentionVSAvoidmemory array structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements local quality by creating region-specific structures within the memory array, such as localized conductive regions and selectively positioned memory cells. This ensures precise electrical coupling in critical areas while simplifying non-critical regions, thereby improving data retention without uniformly increasing complexity across the entire array

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The memory array employs nested structures where conductive vias are embedded within insulating layers, which themselves are embedded within larger memory cell structures. This nesting approach ensures reliable electrical connections at multiple levels while organizing complexity in a hierarchical manner that improves reliability

Inventive Principle:

Principle #7Nested doll (Nesting)

3Manufacturing precision

If through-array vias are not properly formed, then manufacturing steps are reduced, but electrical connectivity and structural integrity deteriorate

Engineering Contradiction:

Improvevia formation accuracyVSAvoidmanufacturing efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent ensures continuity of useful action by implementing a continuous flow manufacturing process where via openings are formed, conductive material is deposited, and surfaces are planarized in an uninterrupted sequence. This continuous approach maintains high via formation accuracy while maximizing manufacturing efficiency through process integration

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The patent replaces traditional mechanical via formation methods with deposition-based approaches, where conductive material is deposited conformally onto prepared surfaces and then selectively removed or planarized. This substitution improves via formation precision while maintaining productivity through automated deposition processes

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11915974B2Integrated circuitry, a memory array comprising strings of memory cells, a method used in forming a conductive via, a method used in forming a memory array comprising strings of memory cells

Publication Date: 2024.02.27 MICRON TECHNOLOGY INC

AI summary

Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.