Etch Stop Layer for 3D NAND Vertical Channel Formation
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Solution Overview
Problem
Current methods for forming three-dimensional vertical NAND strings are inefficient due to the difficulty in achieving precise etching profiles, leading to conical active regions and requiring complex, time-consuming processes, which can result in short circuits and etching stoppages.
Innovation Solution
A method involving the use of a sacrificial feature and etch stop layer to form a U-shaped semiconductor channel with alternating layers of materials, allowing for preferential etching to create memory openings and slit trenches without penetrating through the sacrificial feature, thereby improving etching selectivity and reducing the complexity of the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repeated formation of sidewall spacers and etching is used to form active regions, then the active regions can be formed, but the process becomes difficult and time consuming, resulting in roughly conical active region shape
Solution Approach 1:
The patent introduces an etch stop layer and etch through regions before forming the active regions. The etch stop layer is deposited over the substrate, and etch through regions are formed within it, creating a pre-configured structure that guides subsequent etching processes. This preliminary preparation enables precise control of active region shapes without requiring repeated sidewall spacer formation and etching cycles, significantly reducing process time while maintaining manufacturing precision.
2Manufacturing precision
If conventional etching processes are used, then etching can be performed, but precise etching profiles are difficult to achieve, leading to conical active regions and potential short circuits
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary element between the substrate and the active region formation process. This etch stop layer with etch through regions acts as a mediator that enables precise etching profiles by providing a controlled etching barrier. The etch stop layer prevents over-etching and maintains precise dimensional control, thereby reducing the risk of short circuits while achieving the desired etching profiles.
3Manufacturing precision
If complex repeated processes are used to form active regions, then active regions can be formed, but the process complexity increases and etching stoppages occur
Solution Approach 1:
The patent simplifies the overall process complexity by performing preliminary actions - depositing the etch stop layer and forming etch through regions before active region formation. This pre-configured structure serves as a template that guides subsequent etching, eliminating the need for complex repeated sidewall spacer formation and multiple etching cycles. The preliminary preparation reduces process complexity while maintaining manufacturing precision.
4Productivity
If etching proceeds through the entire stack, then complete openings are formed, but the sacrificial feature may be exposed causing short circuits
Solution Approach 1:
The etch stop layer serves as an intermediary barrier that prevents the etching process from proceeding through the entire stack and exposing the sacrificial feature. The etch through regions within the etch stop layer provide controlled pathways that allow etching to proceed to the desired depth without compromising the sacrificial feature. This intermediary structure maintains reliability by preventing short circuits while preserving etching efficiency through the selective etch through regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of U-shaped semiconductor channels with improved etching profiles, reducing the risk of short circuits and simplifying the fabrication process, resulting in more efficient and reliable three-dimensional vertical NAND strings.
Implementation Method 1
etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack
Implementation Method 2
etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material
Data Source
AI summary
A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.