Etch Stop Layer for Controlled Circuit Impedance
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Solution Overview
Problem
The over-etch process in forming circuit patterns is difficult to accurately control, leading to variations in circuit pattern impedance and electrical characteristics from batch to batch, which is undesirable.
Innovation Solution
A method involving patterning a photoresist layer, plating a patterned etch stop layer and conductor layer using a carrier as the electroplating electrode, and laminating with a dielectric material, which allows for selective etching to prevent conductor layers from being etched during carrier removal, ensuring controlled impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an over-etch process is used to remove excess plated copper, then complete removal of excess copper is achieved, but the circuit pattern impedance and electrical characteristics vary from batch to batch due to difficulty in controlling the etching depth
Solution Approach 1:
An etch stop layer is formed on the carrier before plating the conductor layer. This etch stop layer serves as a pre-established barrier that prevents the conductor layer from being etched during the carrier removal process, thereby ensuring consistent conductor layer dimensions and impedance across batches.
Solution Approach 2:
The etch stop layer acts as an intermediary between the carrier and the conductor layer. It selectively protects the conductor layer during etching operations while allowing the carrier to be removed, thus maintaining manufacturing precision without compromising reliability.
2Manufacturing precision
If electroless plating is used to form the conductor layer, then complete coverage is achieved, but additional desmear processes are required which increases manufacturing complexity
Solution Approach 1:
The patent extracts the desmear process step by using an etch stop layer that prevents conductor material from adhering to the carrier during electroplating. This eliminates the need for subsequent desmear operations, reducing manufacturing complexity while maintaining complete conductor layer coverage.
Solution Approach 2:
The etch stop layer is a temporary, disposable layer that serves its protective function during plating and carrier removal, then is removed itself. This simple, sacrificial layer replaces complex desmear processes, reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures consistent circuit pattern impedance by preventing conductor layers from being etched during carrier removal, thereby maintaining controlled cross-sectional dimensions and reducing fabrication costs.
Implementation Method 1
a first patterned etch stop layer is plated on the first carrier and within the circuit pattern artifacts and a first patterned conductor layer is plated on the first patterned etch stop layer. By using the first carrier as the electroplating electrode for plating of the first patterned etch stop layer and the first patterned conductor layer
Implementation Method 2
As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers as well as the first and second carriers, the first and second patterned etch stop layers provide an etch stop for the carrier etch process
Data Source
AI summary
A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.