Etch-Stop Layer Composite for Semiconductor Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating complex metal wiring layers with reduced dimensions and increased density, where existing damascene processes struggle with achieving precise etching and minimizing etch-stop layer thickness without compromising etching selectivity and capacitance in interconnect layers.
Innovation Solution
The use of an etch-stop layer comprising aluminum-based insulating materials, hafnium oxide, zirconium oxide, or titanium oxide, which provides high etching selectivity and allows for a thinner layer, enabling efficient dry etching of interlayer dielectric layers while maintaining the integrity of the etch-stop layer, thereby reducing capacitance in interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional etch-stop layer is used in the damascene process, then etching selectivity is achieved, but the layer thickness cannot be reduced sufficiently, resulting in increased capacitance in interconnect layers
Solution Approach 1:
The patent applies composite materials by forming a multi-layer etch-stop structure comprising a first etch-stop layer (e.g., silicon nitride) and a second etch-stop layer (e.g., silicon oxide) with different dielectric constants. This composite structure enables both thin overall thickness (reducing capacitance) and sufficient etching selectivity through the combination of materials with complementary properties. The first layer provides primary etch stopping while the second layer contributes to selectivity and structural integrity.
2Object-generated harmful factors
If the etch-stop layer thickness is reduced to minimize capacitance, then interconnect layer performance improves, but etching precision and process margin deteriorate
Solution Approach 1:
The multi-layer etch-stop structure with different dielectric constants provides enhanced etching precision through the synergistic effect of constituent layers. The first etch-stop layer (higher dielectric constant) and second etch-stop layer (lower dielectric constant) create distinct etching rates and selectivity profiles, allowing precise control over etching depth and stopping points even when the total thickness is reduced to minimize capacitance.
Solution Approach 2:
The patent utilizes parameter changes by varying the dielectric constant across different layers of the etch-stop structure. By selecting materials with different dielectric constants (e.g., silicon nitride with higher k-value and silicon oxide with lower k-value), the patent optimizes both the electrical performance (capacitance reduction) and the etching process parameters (selectivity and precision) simultaneously.
3Device complexity
If the damascene process is used to fabricate metal wiring layers, then complex interconnect structures are achieved, but etching selectivity and process control become more difficult
Solution Approach 1:
The multi-layer etch-stop structure simplifies the damascene process by providing superior etching selectivity between different interconnect layers. The distinct dielectric constants and material properties of the first and second etch-stop layers enable selective etching with clearer process windows, making it easier to control the formation of complex via and trench structures in multi-layer interconnect systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the process margin for etching, reduces the thickness of the etch-stop layer, and minimizes capacitance in interconnect layers, improving the manufacturing efficiency and performance of semiconductor devices.
Implementation Method 1
provides high etching selectivity and allows for a thinner layer, enabling efficient dry etching of interlayer dielectric layers while maintaining the integrity of the etch-stop layer
Implementation Method 2
minimizes capacitance in interconnect layers
Data Source
AI summary
A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.