Etch Stop Layer for Buried Contact Plug in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor device fabrication methods result in increased contact resistance between bit contact plugs and metal silicide layers due to reduced contact surface area and the presence of contact barrier layers, making it difficult to control contact resistance effectively.
Innovation Solution
A method involving the formation of an etch stop layer between bit line patterns and buried contact plugs, which prevents damage to conductive patterns below the bit lines and ensures a larger contact surface area by using an etch stop layer to protect the metal silicide layer during etching, allowing for the formation of a buried contact plug with sufficient alignment and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an isotropic etching process is used to extend the buried contact hole, then the contact hole can be extended effectively, but the metal silicide layer is partially etched due to its high etch rate, forming an air gap and reducing contact area
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the upper interlayer dielectric layer and the metal silicide layer. This etch stop layer has a lower etch rate than the metal silicide layer, causing the etching front to pause at this layer and prevent further etching of the metal silicide layer, thereby eliminating the air gap formation while still allowing effective extension of the buried contact hole through the dielectric layers
Solution Approach 2:
The etch stop layer is formed in advance before the buried contact hole extension process. This preliminary action ensures that when the isotropic etching is performed to extend the contact hole, the metal silicide layer is already protected by the etch stop layer, preventing the harmful etching effect before it can occur
2Device complexity
If the bit line pattern is formed directly on the lower interlayer dielectric layer, then the fabrication process is simpler, but the conductive pattern below the bit line may be damaged during subsequent etching processes
Solution Approach 1:
The etch stop layer is formed in advance on the lower interlayer dielectric layer before the bit line pattern is created. This preliminary protective layer remains in place during subsequent etching processes, shielding the conductive pattern below the bit line from damage while allowing the bit line fabrication to proceed with standard processes
Solution Approach 2:
The etch stop layer acts as a cushioning layer that absorbs or prevents the harmful effects of etching processes on the underlying conductive pattern. This beforehand protection ensures that even if aggressive etching is used for bit line formation, the sensitive conductive patterns below remain intact
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and ensures a sufficient contact area between the buried contact plug and the landing pad, while minimizing damage to the metal silicide layer, thereby improving the reliability and performance of semiconductor devices.
Implementation Method 1
the etch stop layer has a lower etch rate than the metal silicide layer, so that an etching front formed during an etching process to form a contact hole between the bit line patterns pauses at the etch stop layer
Data Source
AI summary
In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns. An upper interlayer dielectric layer filling a gap region between the interconnection patterns is formed on the etch stop layer. The upper interlayer dielectric layer is patterned to form a preliminary contact hole between the interconnection patterns, where the etch stop layer is exposed at the bottom of the preliminary contact hole. The preliminary contact hole is extended and the etch stop layer exposed by the extended preliminary contact hole is removed to form a first contact hole exposing the first landing pad. A buried contact plug is then formed within the first contact hole.