Etch Stop Layer for Precise Junction Placement in Vertical Semiconductor Devices
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Solution Overview
Problem
Current methods for forming vertical semiconductor devices, such as FinFETs and tunnel FETs, face challenges in precise junction alignment due to process variability, leading to performance issues like increased source-side resistance and parasitic capacitance, which affect device efficiency.
Innovation Solution
Incorporating a semiconductor etch stop layer within the source or drain regions to control junction alignment by selectively etching the material stack, ensuring precise overlap between the source/drain and channel regions, thereby improving junction placement and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar FET scaling is used, then device dimensions are reduced, but manufacturing precision deteriorates due to process variability affecting junction alignment
Solution Approach 1:
An etch stop layer is deposited within the source or drain region before the channel region is etched. This preliminary action creates a predetermined termination point that guides the etching process, ensuring that the channel region is etched to the correct depth to achieve proper junction alignment with the source/drain regions, thereby resolving the manufacturing precision issue while maintaining scaled dimensions
Solution Approach 2:
The etch stop layer acts as an intermediary element between the source/drain regions and the channel region. By introducing this intermediate layer with distinct etch characteristics, the patent enables precise control over the etching depth, allowing the channel region to be etched selectively to the appropriate depth for optimal junction alignment, thus resolving the alignment precision problem
2Manufacturing precision
If precise junction alignment is achieved through process control, then manufacturing complexity increases, but junction placement precision improves
Solution Approach 1:
The etch stop layer enables the etching process to self-regulate by automatically terminating at the predetermined depth where the channel region should end. This self-service mechanism eliminates the need for complex real-time monitoring and adjustment systems, achieving precise junction placement through the inherent properties of the etch stop layer rather than through complex process control
3Manufacturing precision
If etch stop layer is introduced to control junction alignment, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent introduces an etch stop layer by changing the material composition parameter within the source or drain region. This parameter change creates a layer with distinct etch characteristics that serves as a depth reference during channel etching, improving junction alignment precision while adding minimal structural complexity since the layer is integrated into the existing device architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of an etch stop layer enables precise control over junction alignment, reducing source-side resistance and parasitic capacitance, enhancing the overall performance and efficiency of vertical semiconductor devices like FinFETs and tunnel FETs.
Implementation Method 1
The material stack is etched to provide a channel region selectively to the semiconductor etch stop layer, wherein a depth of the semiconductor etch stop layer dictates overlap between said first of the source or drain region and the channel region of the device
Data Source
AI summary
A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.