Etch Stop Layer for MTJ Device Protection in MRAM Fabrication

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Solution Overview

Problem

The fabrication of magnetic tunnel junction (MTJ) devices in MRAM technology faces challenges in forming a good electrical contact between the top electrode and the interconnect wire, leading to potential damage of the MTJ device and increased costs due to over-etching and overlay errors.

Innovation Solution

An etch stop layer is introduced over the MTJ device to prevent damage during the formation of the upper interconnect wire, allowing for separate processes to expose and remove the etch stop layer, thereby enabling the formation of an upper interconnect wire without significantly damaging the MTJ device, improving the process window and reducing fabrication costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If direct etching is used to form interconnect wire, then fabrication process is simple, but MTJ device is damaged due to over-etching

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidMTJ device integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An etch stop layer is deposited over the MTJ device before forming the upper interconnect wire. This preliminary action creates a protective barrier that prevents over-etching damage to the MTJ device during subsequent etching processes to form the upper interconnect wire.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer acts as an intermediary protective layer between the MTJ device and the etching process. It is selectively removed after serving its protective function, allowing the upper interconnect wire to be formed without directly exposing the MTJ device to harmful etchants.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If conventional formation process is used, then process steps are fewer, but overlay errors increase

Engineering Contradiction:
Improvenumber of process stepsVSAvoidoverlay accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etch stop layer is deposited in advance to establish a precise reference plane for subsequent patterning steps. This preliminary action enables better alignment control and reduces overlay errors when forming the upper interconnect wire and associated structures.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If protective measures are added to prevent MTJ damage, then device reliability improves, but fabrication cost increases

Engineering Contradiction:
ImproveMTJ device protectionVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The etch stop layer is deposited early in the process to provide protection throughout subsequent fabrication steps. This single preliminary protective measure replaces multiple complex protective measures that would otherwise be needed, actually simplifying the overall fabrication process while maintaining device reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer is temporarily introduced to provide protection during critical fabrication steps, then selectively removed when no longer needed. This temporary protective measure prevents permanent damage to the MTJ device without requiring permanent structural modifications, thereby reducing overall process complexity.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS11380580B2Etch stop layer for memory device formation
Publication Date: 2022.07.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11380580B2 patent drawing
  • US11380580B2 patent drawing
  • US11380580B2 patent drawing

AI summary

The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.