Etch Stop Layer Self-Alignment in Display Panel Manufacturing
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Solution Overview
Problem
The high cost of LCD panel manufacturing is attributed to the need for a precise mask alignment during the formation of etch stop layers, which increases the complexity and expense of the process.
Innovation Solution
A method is introduced where a silicon oxide etch stop layer is used, with a controlled dry etch process to form an etch stop pattern that protects the channel area of the semiconductor pattern, allowing for precise control and reduction in the size of the etch stop layer, thereby simplifying the alignment process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a specific mask is used to align the etch stop layer with the channel layer, then the channel layer protection is improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
The etch stop layer itself serves as the alignment reference for forming the semiconductor pattern. By designing the etch stop layer with specific geometric features that directly define the channel area boundaries, the system eliminates the need for external masks - the etch stop layer performs the dual function of both protecting the channel and guiding the patterning process.
Solution Approach 2:
The masking step is extracted and eliminated from the manufacturing process. Instead of adding a separate mask layer for alignment, the patent uses the etch stop layer's own structure to define the pattern, removing the unnecessary masking step while maintaining precise alignment.
2Manufacturing precision
If a mask is precisely aligned with the channel layer, then the etching precision is improved, but the manufacturing cost increases
Solution Approach 1:
The etch stop layer provides self-alignment by having its geometric features directly define the semiconductor pattern boundaries. This self-referential approach eliminates the need for costly precise mask alignment operations while maintaining high etching precision.
Solution Approach 2:
The etch stop layer is formed first with predetermined geometric features that pre-establish the alignment reference. This preliminary structuring eliminates the need for subsequent costly mask alignment operations, as the reference is already in place before semiconductor patterning begins.
3Manufacturing precision
If the etch stop layer size is reduced for precise control, then the channel area protection is improved, but the alignment difficulty increases
Solution Approach 1:
The etch stop layer's reduced size is precisely controlled by using its own geometric features as the direct pattern definition. The same structural features that define the small etch stop area also serve as the alignment reference, eliminating complex alignment procedures despite the reduced dimensions.
Solution Approach 2:
The etch stop layer employs asymmetric geometric features (such as protrusions or notches) that provide unique alignment references. These asymmetric features enable precise positioning and size control of the reduced etch stop layer without requiring complex symmetric alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by enabling precise control over the etch stop layer size and simplifying the alignment process, enhancing the efficiency of LCD panel production without compromising the protection of the channel area during etching.
Implementation Method 1
a controlled dry etch process to form an etch stop pattern
Data Source
AI summary
A display panel manufacturing method includes forming a gate electrode on a substrate and a gate insulator, a semiconductor layer, and an etch stop layer covering the gate electrode. A photoresist layer covering on the etch stop layer is pattern from two opposite side of the substrate by two photolithography processes to form a photoresist pattern. The etch stop layer is dry etched to form an etch stop pattern via the photoresist pattern. The photoresist pattern is formed again by two photolithography processes. The semiconductor layer is wet etched to form a semiconductor pattern via the photoresist pattern. A source electrode and a drain electrode is formed corresponding to two opposite sides of the gate electrode to orderly cover the etch pattern, the semiconductor pattern, and the gate insulator.