Etch Stop Layer Stack for Transistor Strain Engineering
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Solution Overview
Problem
Current CMOS technology faces challenges in creating different strains in transistor channel regions without damaging metal silicide regions, leading to reduced performance and increased production costs due to complex process requirements and potential yield reduction.
Innovation Solution
The use of differently stressed contact etch stop layers, separated by a thin liner, to induce specific strains in channel regions of transistors, reducing damage to metal silicide regions and allowing for efficient strain control without degrading other device features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differently stressed etch stop layers are formed directly on transistor structures to create strain in channel regions, then charge carrier mobility is improved, but metal silicide regions are damaged
Solution Approach 1:
A thin liner layer is introduced as an intermediary between the differently stressed etch stop layers and the transistor structures. This liner layer acts as a protective mediator that prevents direct contact between the etch stop layers and the metal silicide regions, thereby eliminating damage to the metal silicide regions while still allowing the strain effect to be transmitted to the channel regions through the semiconductor material.
2Reliability
If complex process techniques are used to create different strains in channel regions, then transistor performance is improved, but manufacturing complexity and production costs increase
Solution Approach 1:
The etch stop layers are formed with different intrinsic stresses during a single deposition process, allowing them to serve multiple functions: they act as etch stop layers for subsequent processing steps and simultaneously function as strain-inducing layers for the channel regions. This multi-functionality eliminates the need for separate strain engineering process steps, thereby reducing manufacturing complexity while maintaining the ability to create different strains in NMOS and PMOS transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient creation of different strains in transistor channel regions, minimizing damage to metal silicide regions and maintaining high performance, thus improving transistor efficiency and reducing production costs.
Implementation Method 1
creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress
Data Source
AI summary
A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.