Etch Stop Layer Thickness Control in Fin Gate Stack Fabrication
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining structural integrity and functionality.
Innovation Solution
A method involving the formation of fins on a semiconductor substrate, followed by the deposition of a dummy gate dielectric and electrode, patterning, and the use of an anisotropic atomic layer deposition process to create a non-conformal etch stop layer, enhancing the precision and quality of semiconductor device fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form etch stop layers, then the deposition process is simpler and faster, but the thickness uniformity and control precision deteriorate
Solution Approach 1:
The patent employs periodic pulsing of precursors in atomic layer deposition (ALD) to form the etch stop layer. The process alternates between introducing a silicon-containing precursor and a nitrogen-containing precursor in repeated cycles, allowing precise control over layer thickness and composition through the number of pulses applied.
Solution Approach 2:
The patent utilizes parameter changes by varying the number of ALD pulses, precursor flow rates, and deposition temperature to control the etch stop layer thickness and properties. The process transitions from conventional continuous deposition to pulsed ALD with specific timing parameters to achieve superior thickness control.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but manufacturing precision and structural integrity deteriorate
Solution Approach 1:
The patent creates local quality variations by forming a non-conformal etch stop layer with different thicknesses in different locations. The layer is thicker in some regions and thinner in others, providing localized protection during subsequent etching processes to ensure precise feature formation at reduced dimensions.
Solution Approach 2:
The patent addresses dimensional challenges by introducing vertical thickness variation in the etch stop layer as an additional degree of freedom. Instead of relying solely on lateral feature size reduction, the process uses vertical layer thickness modulation to control etching behavior and maintain precision at smaller feature sizes.
3Reliability
If a conformal etch stop layer is deposited, then the deposition process is simpler, but the ability to protect specific regions during etching deteriorates
Solution Approach 1:
The patent deliberately creates an asymmetric, non-conformal etch stop layer structure where the layer thickness varies across different regions. This asymmetric deposition provides differential protection during etching, with thicker regions offering enhanced protection and thinner regions allowing controlled exposure, thereby improving feature definition reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-quality etch stop layers with controlled thickness variations, improving the integration density and reliability of semiconductor devices by ensuring precise feature formation and structural integrity.
Implementation Method 1
depositing an etch stop layer over the gate stack and adjacent to the spacers, the depositing the etch stop layer including: pulsing a first precursor over the gate stack, the first precursor being a non-plasma; and after the pulsing the first precursor, pulsing a second precursor over the gate stack, the second precursor being a plasma
Data Source
AI summary
An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.