Etch-Stop Layer Topography for 10nm IC Fabrication
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Solution Overview
Problem
The scaling of integrated circuits to the 10 nanometer node and beyond is hindered by variability in conventional fabrication processes, limiting the ability to further miniaturize semiconductor features and optimize device performance.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor fabrication, combined with advanced trench isolation and fin trim processes, to create more densely packed and strained semiconductor fins, enabling improved transistor density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and smaller
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows each step to be optimized independently for precision while maintaining overall process manageability at the 10 nanometer node
Solution Approach 2:
Different regions of the semiconductor structure receive different treatments: merged fin regions undergo specific strain engineering and doping, while non-merged fins maintain original characteristics. The epitaxial growth and doping are applied locally to specific trenches and fin regions, enabling precise control of electrical properties in different areas to achieve the required manufacturing precision
2Quantity of substance
If pitch quartering and merged fin pitch quartering approaches are implemented, then transistor density improves, but device complexity increases
Solution Approach 1:
Adjacent fins are merged in specific regions to create merged fin structures that increase local transistor density. The process combines multiple fins into unified structures through selective epitaxial growth and doping, achieving higher density while managing structural complexity through controlled merging rather than treating each fin independently
Solution Approach 2:
The fabrication employs nested trench structures where a first trench extends to a first depth and a second trench extends to a greater second depth within the substrate. This nested arrangement allows multiple isolation and doping regions to be created at different levels, enabling high transistor density without proportionally increasing surface area and structural complexity
3Quantity of substance
If fins are densely packed, then transistor density improves, but strain maintenance becomes difficult
Solution Approach 1:
Strain engineering is performed preliminarily during the epitaxial growth stage before subsequent processing steps. The selective epitaxial growth in the first trench region introduces strain into the fin structures in advance, and this strain is maintained through the subsequent doping and processing steps, ensuring strain is present when transistors are fully formed despite dense packing
Solution Approach 2:
Strain engineering is applied locally to specific fin regions through selective epitaxial growth and doping in the first trench, while other regions maintain different properties. This local application of strain allows dense overall packing while preserving necessary strain in critical transistor regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques allow for the fabrication of densely packed semiconductor fins with maintained strain, enhancing transistor density and performance, addressing the limitations of conventional processes in miniaturization and optimization for advanced integrated circuit structures.
Implementation Method 1
densely packed and strained semiconductor fins, enabling improved transistor density and performance
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.