Etch Stop Layers for III-V MOSFET Source/Drain Recesses
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Solution Overview
Problem
The deposition of III-V material fins on silicon substrates is challenging due to lattice mismatch, leading to high defect densities and poor etch selectivity, which degrades transistor performance in III-V MOSFETs.
Innovation Solution
A buffer layer and a first III-V semiconductor layer are deposited on a substrate, with the first layer acting as an etch stop to accurately control the formation of source/drain recesses and fin release, and an InP bottom capping layer is used to reduce lattice mismatch and enhance etch selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a GaAs buffer layer is grown directly on a silicon substrate to enable III-V material deposition, then the III-V material can be deposited on silicon, but the large lattice mismatch between GaAs and silicon results in high defect densities that reduce carrier mobility and degrade transistor performance
Solution Approach 1:
The patent segments the buffer layer structure into multiple distinct layers: a silicon oxide layer directly on silicon, a graded InGaAs layer, and a GaAs layer. This segmentation allows each layer to serve a specific function - the silicon oxide provides a controlled interface, the graded InGaAs gradually transitions the lattice constant, and the GaAs provides the final III-V platform, thereby reducing defect propagation while enabling III-V deposition on silicon.
Solution Approach 2:
The patent employs parameter changes by using a graded InGaAs buffer layer where the indium composition is gradually varied. This compositional gradient changes the lattice constant progressively, accommodating the mismatch between silicon and GaAs, thereby reducing dislocation densities and improving material quality without sacrificing the ability to deposit III-V materials on silicon.
2Reliability
If an InGaAs channel layer is grown on a GaAs buffer layer to achieve high electron mobility, then carrier mobility improves, but the large lattice mismatch between GaAs and InGaAs creates high defect densities that reduce mobility and degrade performance
Solution Approach 1:
The patent uses a graded InGaAs buffer layer with varying indium composition to gradually transition the lattice constant between GaAs and InGaAs channel layers. This parameter change approach reduces lattice mismatch and minimizes dislocation densities, thereby maintaining high carrier mobility while reducing defect densities in the InGaAs channel layer.
3Ease of manufacture
If a GaAs buffer layer is used to grow InGaAs channel layer, then III-V material deposition is enabled, but the system has poor etch selectivity making source/drain recess etching and fin release difficult to control
Solution Approach 1:
The patent segments the buffer structure to include a silicon oxide layer beneath the InGaAs/GaAs layers. This silicon oxide layer serves as an etch stop layer that provides excellent etch selectivity, allowing precise control of source/drain recess etching and fin release processes while maintaining the III-V material deposition capability on silicon substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defect densities, improves etch control, and decreases parasitic source/drain resistance, leading to higher crystalline quality and reduced leakage current in III-V MOSFETs.
Implementation Method 1
the first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion
Implementation Method 2
A large lattice mismatch between the III-V material and silicon results in high defect densities in the III-V material grown on Si
Data Source
AI summary
A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.