Etch-Stop Tier for Vertical Memory Channel Control
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Solution Overview
Problem
Current methods for forming arrays of elevationally-extending strings of memory cells, such as NAND cells, face challenges in achieving precise control over channel openings and critical dimension control, leading to potential radially inward tapering and reduced efficiency in data storage.
Innovation Solution
The use of a 'gate-last' or 'replacement-gate' processing method involving an etch-stop tier of different composition, which is selectively etched to form channel openings that improve critical dimension control and reduce tapering, allowing for the formation of vertical or near-vertical strings of transistors and memory cells with appropriate charge-blocking and charge-storage materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form channel openings, then the manufacturing process is simpler, but critical dimension control deteriorates and radially inward tapering occurs
Solution Approach 1:
An etch-stop tier is formed in advance within the insulative tiers before the channel opening etching process. This preliminary structure serves as a reference plane that prevents radially inward tapering during subsequent etching operations, thereby improving critical dimension control without requiring complex real-time process adjustments.
Solution Approach 2:
The etch-stop tier acts as an intermediary reference structure between the insulative tiers and the channel openings. By providing a stable intermediate plane, it enables precise control of channel opening dimensions and prevents tapering, resolving the contradiction between manufacturing precision and process complexity.
2Productivity
If channel openings are formed without an etch-stop tier, then the process is faster, but radially inward tapering reduces data storage efficiency
Solution Approach 1:
The etch-stop tier is prepared in advance as a reference structure before channel opening formation. This allows standard etching processes to be used while achieving consistent, non-tapered channel openings, thereby maintaining both formation speed and data storage efficiency.
Solution Approach 2:
By introducing the etch-stop tier, the reference plane for etching is changed from the variable insulative tier surfaces to a stable, predetermined plane. This parameter change ensures uniform channel opening dimensions and prevents tapering, maintaining reliability without significantly impacting productivity.
3Ease of manufacture
If the insulative tiers are etched directly to form channel openings, then fewer process steps are required, but precise control over opening dimensions is lost
Solution Approach 1:
The etch-stop tier serves as an intermediary reference structure that simplifies the manufacturing process by providing a stable etching reference plane. This eliminates the need for complex real-time dimension control mechanisms while ensuring precise opening dimensions, thus resolving the contradiction between process simplicity and manufacturing precision.
Solution Approach 2:
The introduction of the etch-stop tier changes the reference parameter for etching from the variable insulative tier thickness to a fixed, predetermined plane. This parameter change enables precise dimension control while maintaining process simplicity, as standard etching procedures can be used without complex feedback control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the formation of efficient elevationally-extending strings of memory cells by improving critical dimension control and reducing undesired tapering, thereby improving data storage efficiency and reliability.
Implementation Method 1
Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings
Data Source
AI summary
A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.