Multi-Layer Etch Stop Structure for Via Corrosion Control
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Solution Overview
Problem
Integrated circuits (ICs) face defects such as via-induced metal island corrosion (VIMIC) due to hillocks on conductive wires and pin holes in the etch stop layer during plasma etching, leading to reduced reliability and performance of electrical connections between capacitors and interconnect structures.
Innovation Solution
An etch stop structure comprising a first etch stop layer, a first insulator layer, and a second etch stop layer is disposed along conductive wires, with specific thicknesses and materials to mitigate hillock formation and pin hole creation during plasma etching, thereby reducing galvanic corrosion and diffusion of conductive materials during wet etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single etch stop layer is used during plasma etching, then the etching process can be completed, but hillocks form on conductive wires and pin holes appear in the etch stop layer, causing galvanic corrosion and reducing reliability
Solution Approach 1:
The single etch stop layer is divided into multiple etch stop layers with different materials and thicknesses. The first etch stop layer (50-750 Å) protects against hillock formation, the second etch stop layer (200-500 Å) prevents pin hole creation, and intermediate insulator layers provide additional protection. This segmented structure resolves the contradiction by distributing the protective function across multiple specialized layers.
Solution Approach 2:
The etch stop structure uses composite materials consisting of alternating etch stop layers (silicon nitride, silicon carbide, or silicon carbon-nitride) and insulator layers (silicon dioxide, phosphosilicate glass, or borophosphosilicate glass). This composite structure provides both hillock prevention and pin hole prevention while maintaining etch selectivity and electrical insulation properties.
2Reliability
If plasma etching is performed to create conductive vias, then electrical connections can be established, but galvanic corrosion and diffusion of conductive materials occur during subsequent wet etching
Solution Approach 1:
The multi-layer etch stop structure is formed beforehand to cushion and prevent damage during subsequent wet etching processes. The etch stop layers act as a protective barrier that prevents galvanic corrosion and material diffusion before these harmful effects can occur, thereby resolving the contradiction between establishing electrical connections and preventing corrosion.
3Reliability
If the etch stop layer thickness is increased to prevent pin holes, then protection against corrosion improves, but the formation of hillocks on conductive wires increases
Solution Approach 1:
Instead of using a single thick etch stop layer that causes hillock formation, the protective function is segmented into multiple thinner layers. The first etch stop layer (50-750 Å) provides baseline protection, while intermediate insulator layers and a second etch stop layer (200-500 Å) provide additional protection against pin holes without requiring excessive thickness in any single layer, thus preventing hillock formation while maintaining corrosion protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the reliability and performance of electrical connections by reducing defects in the interconnect structure, increasing the yield and endurance of ICs by minimizing damage to conductive wires and vias.
Implementation Method 1
hillocks on conductive wires and pin holes in the etch stop layer during plasma etching
Implementation Method 2
reducing galvanic corrosion and diffusion of conductive materials during wet etching
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a plurality of conductive contacts overlying a semiconductor substrate. A plurality of first conductive wires is disposed on the plurality of conductive contacts. A plurality of conductive vias overlies the first conductive wires. An etch stop structure is disposed on the first conductive wires. The plurality of conductive vias extend through the etch stop structure. The etch stop structure includes a first etch stop layer, a first insulator layer, and a second etch stop layer. The first insulator layer is disposed between the first etch stop layer and the second etch stop layer.