Etch Stop Layer Self-Aligned Via Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of features in integrated circuits poses challenges in via fabrication, particularly with extremely small via pitches and critical dimensions, as current lithographic processes struggle to maintain overlay tolerances, line width roughness, and critical dimension uniformity, and are limited by the resolution capabilities of equipment and photoresist characteristics.
Innovation Solution
The use of etch stop layers for directed self-assembly and selective deposition enables self-aligned conductive via formation, improving via shorting margins and reducing alignment errors through surface treatments and bilayer etch stop layers, allowing for continued scaling beyond conventional lithography limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used for via fabrication, then existing manufacturing capabilities are maintained, but overlay tolerances and alignment precision deteriorate as via pitches scale to 70-90 nm or less
Solution Approach 1:
The patent segments the via formation process into multiple steps: first forming mandrels at relaxed pitch, then using spacer deposition and selective removal to create final via openings. This segmentation allows the lithographic step to work at larger dimensions while achieving smaller final via pitches through self-aligned spacer formation, thereby maintaining overlay tolerances despite scaling.
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between the lithographically formed mandrels and the final via openings. These spacers serve as self-aligned masks that define the via locations with precision independent of lithographic overlay errors, enabling accurate via formation at small pitches.
2Length of moving object
If shrink technologies are applied to reduce via opening critical dimensions, then via size is reduced, but line width roughness and critical dimension uniformity deteriorate
Solution Approach 1:
The spacer structures form through self-aligned deposition processes where the spacer material automatically conforms to the mandrel sidewalls. This self-aligned formation mechanism inherently ensures uniform spacer thickness and consistent via opening dimensions without requiring additional alignment steps, thereby maintaining critical dimension uniformity while achieving small via sizes.
3Manufacturing precision
If multiple lithographic masks are used to achieve extremely small via pitches, then via pitch resolution is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent performs preliminary action by forming mandrels at relaxed pitch using standard lithography, then uses spacer deposition to achieve the final fine pitch. This preliminary mandrel formation at larger dimensions avoids the need for multiple high-resolution lithographic masks, simplifying the manufacturing process while achieving the required small via pitches.
Data Source
AI summary
Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.