Etch Stop Layer Via Faceting Control in Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor devices continue to shrink, challenges arise in creating high-performance interconnect structures due to issues like loss of mask material, constrained process windows, and inconsistencies in via profiles, particularly in the fabrication of interconnects with smaller critical dimension sizes.
Innovation Solution
The introduction of an added etch stop layer around the junction of a via and a trench in the interconnect structure, which serves as a hard mask to facilitate precise patterning and filling with conductive material, improving via faceting control and addressing the challenges of smaller critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional interconnect structures are used with smaller critical dimension sizes, then device scaling is achieved, but mask material loss and via profile inconsistencies occur
Solution Approach 1:
The patent applies preliminary action by forming the etch stop layer before the via etching process. This pre-formed layer serves as a protective barrier that prevents mask material loss during subsequent etching operations, while still allowing the via to be etched to the required smaller critical dimension size.
Solution Approach 2:
The etch stop layer acts as an intermediary element between the mask layer and the underlying substrate. It mediates the etching process by providing a controlled interface that prevents direct interaction between the etchant and the mask material, thereby reducing mask material loss while maintaining via profile consistency.
2Length of moving object
If conventional interconnect structures are used with smaller critical dimension sizes, then device scaling is achieved, but via profile inconsistencies arise
Solution Approach 1:
The etch stop layer is formed in advance to establish a controlled etching interface. This preliminary structure ensures that the via etching process proceeds with consistent parameters, producing uniform via profiles even at smaller critical dimension sizes.
Solution Approach 2:
The patent introduces an additional layer that changes the etching parameters at the via interface. This modification to the etching environment ensures consistent via profile formation by controlling the etch rate and selectivity, thereby improving manufacturing precision at scaled dimensions.
3Manufacturing precision
If additional etch stop layer is added to improve via faceting control, then via profile consistency is improved, but device complexity increases
Solution Approach 1:
The patent segments the interconnect structure by adding a dedicated etch stop layer as a separate functional component. This segmentation allows independent optimization of via faceting control without affecting other parts of the interconnect structure, managing complexity through functional decomposition.
Solution Approach 2:
The etch stop layer serves multiple functions: it controls via faceting, defines etch boundaries, and provides a reference plane for subsequent processing steps. This multi-functionality reduces the need for additional separate layers or structures, thereby managing overall device complexity while achieving improved via profile control.
Data Source
AI summary
A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.