Etched Foil Capacitors Integrated into Semiconductor Leadframes
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Solution Overview
Problem
Traditional semiconductor package fabrication methods limit the integration of multiple capacitors within small leadframe-based packages, leading to increased parasitic resistances and costs due to the placement of discrete capacitors as piece parts on the board.
Innovation Solution
A process flow that integrates etched foil capacitors with the leadframe by forming and patterning them before the leadframe, allowing for the inclusion of an arbitrary number of high-capacitance capacitors within the package, where aluminum foil is etched to create pores, filled with a conductive polymeric compound, and the leadframe is patterned simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete capacitors are placed on the board near the device, then the required capacitance can be achieved, but parasitic resistances increase and board space is consumed
Solution Approach 1:
The patent merges the capacitor function with the leadframe structure by integrating etched foil capacitors directly into the package. The leadframe serves dual purposes as both the mechanical support structure and as the capacitor substrate, eliminating the need for separate discrete capacitors on the board.
Solution Approach 2:
The patent utilizes the third dimension by creating folded capacitor structures within the leadframe plane. The etched foil capacitors are formed with multiple folded layers that stack vertically, achieving high capacitance values within the limited two-dimensional footprint of the package.
2Ease of manufacture
If only one or few capacitors are integrated into the package, then the fabrication process remains simple, but multiple discrete capacitors must be placed on the board increasing complexity and cost
Solution Approach 1:
The patent performs preliminary action by pre-forming multiple capacitor structures directly on the leadframe during the leadframe fabrication process itself. The etched foil capacitors are created before package assembly, allowing multiple capacitors to be integrated simultaneously without adding separate assembly steps.
3Quantity of substance
If the leadframe area is fully utilized for capacitor integration, then more capacitors can be placed in the package, but the leadframe pattern becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the leadframe into distinct functional zones: capacitor regions with etched foil patterns and leadframe regions with standard lead patterns. This segmentation allows each region to be optimized independently, maintaining simple leadframe patterns while achieving high capacitor integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of multiple capacitors within semiconductor packages, reducing parasitic resistances and costs by directly placing high-capacitance components where needed, while maintaining the conventional packaging steps.
Implementation Method 1
Pores are created in the aluminum by etching
Implementation Method 2
the aluminum surface in the cavities is then oxidized
Data Source
AI summary
A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.