Semiconductor Package Contacts With Etched Notches for Crack-Free Dies

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Solution Overview

Problem

Conventional semiconductor package manufacturing methods, particularly sawing techniques, lead to chipping and cracking of semiconductor dies, compromising their reliability and limiting package shape flexibility.

Innovation Solution

Employing etching techniques to form notches in semiconductor wafers, which allows for crack-free and shape-diverse semiconductor packages, coupled with a mold compound for protection and anchoring, and metal layers for electrical contacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sawing techniques are used to manufacture semiconductor packages, then manufacturing efficiency is improved, but chipping and cracking of semiconductor dies occur

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoiddie integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent replaces the mechanical sawing process with a chemical etching process to form notches in the semiconductor wafer. This substitution eliminates the mechanical contact that causes chipping and cracking, thereby maintaining manufacturing efficiency while improving die integrity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the manufacturing parameter from mechanical cutting to chemical etching. By altering the fundamental process parameter from mechanical force to chemical reaction, the method achieves both high productivity and preserved die integrity without the harmful effects of sawing.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If conventional molding is applied to protect semiconductor dies, then environmental protection is improved, but package shape flexibility is limited

Engineering Contradiction:
Improveenvironmental protectionVSAvoidpackage shape flexibility
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent divides the wafer into individual dies using chemical etching to form notches, allowing each die to be independently packaged. This segmentation enables different package shapes and configurations while maintaining the protective molding function, thus improving shape flexibility without compromising environmental protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the molding approach by using chemical etching to define precise die boundaries and shapes before molding. This parameter change from post-cutting molding to pre-defined shape molding enables greater package shape flexibility while maintaining comprehensive environmental protection.

Inventive Principle:
Principle #35Parameter changes

3Volume of moving object

If semiconductor die thickness is decreased to reduce package size, then package compactness is improved, but mechanical strength is reduced

Engineering Contradiction:
Improvepackage sizeVSAvoiddie mechanical strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The patent employs a composite structure where the thinned semiconductor die is combined with a protective molding material and metal interconnect layers. This composite construction provides mechanical strength to the thinned die, enabling reduced package size without sacrificing structural integrity.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies protective molding material before final packaging to cushion and protect the thinned die. This beforehand cushioning compensates for the reduced mechanical strength of thinned dies, allowing package size reduction while maintaining sufficient mechanical strength.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12431359B2Semiconductor package electrical contacts and related methods
Publication Date: 2025.09.30 SEMICON COMPONENTS IND LLC
  • US12431359B2 patent drawing
  • US12431359B2 patent drawing
  • US12431359B2 patent drawing

AI summary

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.