Etched Semiconductor Terminal Geometry for Solder Wettability
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Solution Overview
Problem
Current semiconductor devices face challenges in mounting reliability due to issues with solder wettability and bonding defects, particularly caused by burrs formed during the manufacturing process, which can lead to electrical connection defects.
Innovation Solution
The semiconductor device design incorporates a terminal structure with a metal layer on its lower surfaces and side surfaces, utilizing electrolytic etching to selectively remove burrs and position the lower surfaces of the terminal portions correctly, enhancing solder wettability and increasing the contact area for improved bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrolytic etching is used to remove burrs from terminals, then solder wettability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing electrolytic etching on the terminal surfaces before the soldering process. This pre-treatment removes burrs and oxides in advance, ensuring the terminal surfaces are clean and ready for soldering, thereby improving solder wettability without requiring additional complex equipment during the soldering process itself
Solution Approach 2:
The patent replaces mechanical burr removal methods (such as physical filing or grinding) with electrolytic etching, which uses electrochemical reactions to selectively remove burrs and oxides from the terminal surfaces. This substitution provides a more precise and controllable process that improves surface quality for soldering
2Area of stationary object
If the lower surface of the terminal is positioned lower than the insulating portion, then contact area for bonding is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by controlling the etching depth and duration of the electrolytic etching process to achieve the desired differential positioning between the terminal lower surface and the insulating portion. By adjusting etching parameters (current density, time, electrolyte composition), the terminal surface is selectively recessed to create the required positioning relationship, increasing contact area while maintaining manufacturability
Solution Approach 2:
The electrolytic etching process inherently creates the differential positioning between the terminal and insulating portion through selective material removal. The process automatically achieves the desired geometry where the terminal lower surface becomes lower than the insulating portion, eliminating the need for separate machining operations to create this positioning relationship
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the mounting reliability of semiconductor devices by ensuring better solder wettability and reducing the likelihood of electrical connection defects, allowing for more reliable bonding between the semiconductor device and other components.
Implementation Method 1
utilizing electrolytic etching to selectively remove burrs and position the lower surfaces of the terminal portions correctly
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first conductive part, a semiconductor element, a first terminal, and a metal layer. The semiconductor element is located on the first conductive part. The first terminal is separated from the first conductive part in a second direction perpendicular to a first direction. The first direction is from the first conductive part toward the semiconductor element. The first terminal includes a first portion, and a second portion located between the first portion and the first conductive part. A lower surface of the second portion is positioned lower than a lower surface of the first portion and lower than a lower surface of a first insulating portion. The first insulating portion is located between the first conductive part and the second portion. The metal layer is located at the lower surfaces of the first portion and of the second portion.