Etching Back Method for Dielectric Layer Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In microfabrication, existing etching back methods struggle to achieve a flat top surface in areas with different pattern densities due to varying etching rates and layer thicknesses, leading to step height differences and inefficiencies in semiconductor manufacturing.
Innovation Solution
The method involves forming a substrate with high and low pattern density areas, depositing dielectric layers with different etching rates to fill recesses, and performing an etching back process where the etching rate for the second dielectric layer is lower than for the first, resulting in a flatter top surface after processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single dielectric layer is used to fill recesses in areas with different pattern densities, then the manufacturing process is simple, but the top surface becomes non-flat due to varying etching rates
Solution Approach 1:
The dielectric layer is divided into multiple segments (first dielectric layer and second dielectric layer) with different etching rates. The first dielectric layer has a higher etching rate and the second dielectric layer has a lower etching rate, allowing each layer to compensate for surface non-flatness in different pattern density areas, ultimately achieving a flat top surface.
2Manufacturing precision
If dielectric layers with different thicknesses are deposited to compensate for pattern density variations, then surface flatness is improved, but the manufacturing process becomes more complex
Solution Approach 1:
Different dielectric layers are applied to different regions of the substrate based on pattern density. The first dielectric layer with higher etching rate is used in high pattern density areas, while the second dielectric layer with lower etching rate is used in low pattern density areas, allowing local optimization of surface flatness.
Solution Approach 2:
The patent uses a composite dielectric structure combining multiple dielectric materials with different etching rates. This composite approach allows the layers to work together synergistically, where the higher etching rate layer compensates for non-flatness in high density areas and the lower etching rate layer maintains flatness in low density areas.
3Productivity
If an etching back process with uniform etching rate is applied, then the process is simple and fast, but it cannot achieve flat top surface in areas with different pattern densities
Solution Approach 1:
The etching rate parameter is changed between different dielectric layers. The first dielectric layer is designed with a higher etching rate parameter, while the second dielectric layer has a lower etching rate parameter. This parameter differentiation allows the etching back process to selectively remove material at different rates, achieving flat top surface while maintaining reasonable processing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a flat top surface of the dielectric layer by controlling etching rates and layer thicknesses, improving the precision and efficiency of the etching back process in semiconductor manufacturing.
Implementation Method 1
An etching back process is performed to remove the second dielectric layer and a top part of the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer
Data Source
AI summary
A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.