Etching Compensation for Insulating Layer Trench Uniformity
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Solution Overview
Problem
The challenge in fabricating integrated circuit devices lies in forming patterns with small line widths on semiconductor substrates, where the use of low dielectric constant insulating materials can result in lower device yields due to uncontrolled etching rates, especially when trying to reduce resistance and integrate more densely.
Innovation Solution
The method involves forming an integrated circuit substrate with a low dielectric constant insulating layer, using a mask layer with openings of different sizes to etch the layer at varying rates, and then compensating for these rates by exposing the etched trenches to specific etching gases to achieve trenches of substantially equal depths, ensuring uniformity and preventing yield reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low dielectric constant insulating materials are used to reduce resistance and increase integration density, then productivity and device performance are improved, but manufacturing precision deteriorates due to uncontrolled etching rates
Solution Approach 1:
The patent applies local quality by using different etching gases for different regions. Specifically, a first etching gas (CF4, SF6, or NF3) is used for etching narrow line width regions, while a second etching gas (CHF3, CF3H, or CF3I) is used for etching wide line width regions. This allows the etching process to be locally optimized for each region's specific requirements, achieving uniform trench depths across varying line widths while maintaining the benefits of low dielectric constant materials.
2Productivity
If small line width patterns are formed to increase integration density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in controlling etching uniformity
Solution Approach 1:
The patent implements local quality by selecting etching gases based on the line width region being etched. Narrow line width regions (first regions) are etched using CF4, SF6, or NF3 gases that provide appropriate etch rates and anisotropy for small features. Wide line width regions (second regions) are etched using CHF3, CF3H, or CF3I gases that achieve uniform depths without excessive side wall etching. This regional differentiation ensures consistent pattern quality across the entire wafer despite varying feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield and reliability of semiconductor integrated circuit devices by forming trenches with more uniform depths, even in regions with different line widths, thereby improving the integration density and reducing resistance.
Implementation Method 1
exposing the first and second portions of the electrically insulating layer to a first etching gas including CxFy, where 2x≧y, x>0 and y>0 (e.g., C4F8, C4F6 and C5F8)
Data Source
AI summary
Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.