Etching InGaAs Fin Core for Double Fin Transistors

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Solution Overview

Problem

The deposition of III-V materials on silicon substrates for fin-based transistors is challenging due to lattice mismatch and thermal expansion coefficient differences, leading to high defect densities and reduced carrier mobility, which degrades transistor performance.

Innovation Solution

A method involving the selective etching of a gallium-rich core from an InGaAs fin to create two indium-rich fins, utilizing the etch-selectivity of Ga-rich InGaAs with respect to In-rich InGaAs, resulting in a double fin structure that enhances carrier mobility and transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If III-V material is deposited on silicon substrate for fin-based transistors, then electron mobility is improved, but defect density increases due to lattice mismatch and thermal expansion coefficient differences

Engineering Contradiction:
Improveelectron mobilityVSAvoiddefect density
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The fin structure is segmented into two identical fins by removing the core portion, creating two separate transistor channels that can be independently controlled, effectively doubling the transistor density while maintaining low defect densities through the silicon-germanium sacrificial layer approach

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A silicon-germanium sacrificial layer is introduced as an intermediary material between the silicon substrate and the III-V material fins. This intermediate layer serves as a buffer that reduces lattice mismatch and thermal expansion differences, enabling high-quality III-V material growth on silicon substrate with significantly reduced defect densities

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional epitaxial growth processes are used to grow III-V material fins on silicon, then material quality is improved, but process complexity increases

Engineering Contradiction:
Improvematerial qualityVSAvoidepitaxial growth process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A silicon-germanium sacrificial layer is deposited and then selectively removed to create the fin structure. This disposable sacrificial layer simplifies the overall process by enabling standard CMOS-compatible fabrication steps rather than requiring complex in-situ epitaxial growth, while still achieving high material quality through controlled deposition and etching processes

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If fin-based transistors are used to improve electrostatic control, then short-channel effects are reduced, but manufacturing difficulty increases due to material dissimilarity

Engineering Contradiction:
Improveelectrostatic controlVSAvoidmanufacturing difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The lattice constant and thermal expansion parameters are optimized by using silicon-germanium alloys with varying germanium concentrations. By adjusting the Ge content in the sacrificial layer, the process achieves compatibility with standard CMOS fabrication parameters while maintaining the electrostatic control benefits of fin-based structures

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The silicon-germanium sacrificial layer acts as an intermediary that bridges the material dissimilarity between silicon substrate and III-V fins, enabling standard silicon processing techniques to be used throughout the fabrication process while still achieving the electrostatic control advantages of III-V material fins

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves trans-conductance and mobility of transistors compared to conventional methods, achieving higher performance without the need for complex epitaxial growth processes, and results in high-performing fin-based transistors with increased carrier mobility.

Implementation Method 1

utilizing the etch-selectivity of Ga-rich InGaAs with respect to In-rich InGaAs

Methodology Applied
Scientific EffectEtch-selectivity:

Implementation Method 2

Deposition of the III-V material fin on a silicon substrate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11024737B2Etching fin core to provide fin doubling
Publication Date: 2021.06.01 INTEL CORP
  • US11024737B2 patent drawing
  • US11024737B2 patent drawing
  • US11024737B2 patent drawing

AI summary

A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.