Etching Insulating Layers to Reduce Channel Loss
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Solution Overview
Problem
Existing semiconductor layer formation and etching techniques often result in unintended etching of thin channel regions, leading to variations in transistor properties such as threshold voltage due to the difficulty in precisely controlling the thickness of the silicon device layer.
Innovation Solution
A method involving the sequential deposition and selective etching of insulating layers over a semiconductor device region, using different etching processes to form spacers and prevent etching of the underlying channel region, thereby reducing unintended etching and maintaining the integrity of the channel thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the silicon device layer is thinned to form thinner channels for better transistor control, then transistor operation control is improved, but channel thickness variation increases leading to transistor property variation
Solution Approach 1:
The patent segments the etching process into multiple distinct steps: a first etching process that etches the first insulating layer, and a second etching process that etches the second insulating layer. This segmentation allows each etching process to be optimized independently, with the first process forming spacers and the second process removing sacrificial material without affecting the channel region, thereby preventing channel thickness variation while maintaining good transistor control
Solution Approach 2:
The patent introduces insulating layers (first and second insulating layers) as intermediary protective structures. These layers act as sacrificial spacers that protect the underlying silicon device layer during etching processes. The first insulating layer forms spacers on gate regions, and the second insulating layer serves as an additional protective layer that is removed after serving its protective function, thereby preventing direct etching of the channel region and maintaining precise channel thickness control
2Ease of manufacture
If conventional single etching process is used, then process simplicity is maintained, but unintended etching of channel region occurs causing property variation
Solution Approach 1:
The etching process is divided into a first etching process and a second etching process. The first etching process uses a first etchant to etch the first insulating layer and form spacers, while the second etching process uses a second etchant to etch the second insulating layer and remove sacrificial material. This segmentation prevents unintended etching of the channel region by ensuring that each etching step is targeted and controlled, thereby maintaining channel region integrity while still being manufacturable
Solution Approach 2:
The first and second insulating layers serve as intermediary protective barriers during the etching processes. These sacrificial layers are specifically designed to be etched away after serving their protective function. They prevent the etchants from directly contacting and unintentionally etching the channel region, thus protecting channel region integrity while allowing the etching processes to proceed
Data Source
AI summary
Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.