Etching-Mask Dicing Lines for Clean Edges in Porous Capacitors
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Solution Overview
Problem
The existing methods for forming three-dimensional capacitors in semiconductor products result in jagged and irregular edges during dicing, which can degrade the mechanical properties of integrated devices, and the use of laser grooving introduces additional process steps, costs, and potential damage to the underlying materials.
Innovation Solution
A method involving the formation of a metal barrier layer, an anodizable metal layer, and subsequent anodization to create porous regions with straight pores, followed by etching to form oxide plugs at the bottom ends of pores, which act as anchoring points to prevent splintering during mechanical dicing, allowing for clean and regular dicing lines without the need for laser grooving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mechanical blade dicing is used to dice integrated devices, then productivity is improved, but manufacturing precision deteriorates due to jagged and irregular edges
Solution Approach 1:
The patent applies preliminary action by forming oxide plugs at the bottom ends of pores in the porous regions before the mechanical dicing process. These oxide plugs are created through an anodization process that selectively forms them in the dicing line regions. When the mechanical blade subsequently passes through, the oxide plugs prevent chip splintering and ensure clean, regular edges without requiring additional process steps during or after dicing.
2Manufacturing precision
If laser grooving is performed prior to mechanical blade dicing, then manufacturing precision is improved by preventing chip splintering, but device complexity increases due to additional process steps
Solution Approach 1:
The patent merges the formation of dicing lines with the existing porous structure fabrication process. The oxide plugs that prevent chip splintering are formed during the same anodization process used to create the porous regions for high-capacitance structures. This integration eliminates the need for separate laser grooving or other preliminary dicing preparation steps, reducing process complexity while maintaining edge quality.
Solution Approach 2:
The porous structures serve a dual function: they provide high capacitance density for the integrated devices and simultaneously form dicing lines with oxide plugs that prevent chip splintering during mechanical dicing. The structure essentially serves itself by using the same porous regions that provide electrical function to also define the mechanical dicing paths, eliminating the need for separate dicing preparation processes.
3Reliability
If laser grooving is used to prevent chip splintering, then reliability is improved, but object-affected harmful factors increase due to laser heat damaging underlying materials
Solution Approach 1:
The patent replaces the thermal/mechanical laser grooving process with a chemical anodization process that forms oxide plugs in situ. Instead of using laser heat to prevent chip splintering, the method uses electrochemical oxidation to create porous structures with oxide plugs that mechanically anchor the dicing lines. This substitution eliminates laser-induced thermal damage to underlying materials while maintaining reliability through the oxide plug anchoring mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents the splintering of chips and ensures clean, regular edges during dicing, reducing the risk of mechanical property degradation and eliminating the need for additional process steps, while maintaining the high capacitance density of three-dimensional capacitors.
Implementation Method 1
anodizing a first region and a second region of the anodizable metal layer to obtain respectively a first porous region and a second porous region both comprising a plurality of substantially straight pores that extend from a top surface of the porous region, perpendicularly to the top surface of the porous region, towards the metal barrier layer
Implementation Method 2
etching the bottom ends of pores of the second porous region through the opening of the etching mask to obtain pores that form a device region
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A method for obtaining an integrated device comprising: forming a metal barrier layer (102) above a substrate, forming an anodizable metal layer on the metal barrier layer, anodizing a first region and a second region of the anodizable metal layer to obtain respectively a first porous region (PRA) and a second porous region (PRB) both comprising a plurality of substantially straight pores (105) that extend from a top surface of the porous region, perpendicularly to the top surface of the porous region, towards the metal barrier layer, forming an etching mask (107) above at least the first porous region (PRA) having an opening (OP) above the second porous region, etching the bottom ends of pores of the second porous region through the opening of the etching mask to obtain pores that form a device region, and pores in the first porous region that form a dicing line, the integrated device being delimited at least by the dicing line.