Etching Metal Stacks with Fluorine Recipes to Reduce Micromasking
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Solution Overview
Problem
The existing methods for etching metal stacks in semiconductor processing often result in significant micromasking residue at the hard mask layer/barrier layer interface, leading to undesirable short circuits between metal interconnect lines, and require additional oxygen-deficient layers or washing steps to mitigate this issue, which can decrease efficiency and increase costs.
Innovation Solution
Employing a fluorine-containing etch recipe, specifically using CF4 and CHF3, to etch through the interface between the hard mask layer and the barrier layer, thereby reducing micromasking residue without the need for additional oxygen-deficient layers or washing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If oxide-based hard mask layer is used for etching metal stacks, then the hard mask strength is improved to withstand harsh etching processes, but micromasking residue is generated at the hard mask/barrier layer interface causing short circuits
Solution Approach 1:
The patent changes the chemical composition parameters of the hard mask layer by forming a silicon-rich oxide layer (with Si:O ratio greater than 1:2) instead of a stoichiometric oxide layer. This parameter change in the material composition prevents micromasking residue formation while maintaining the necessary etch resistance, thereby resolving the contradiction between hard mask strength and micromasking residue generation.
2Reliability
If washing steps or oxygen-deficient layers are added to remove micromasking residue, then the short circuit defects are reduced, but the processing efficiency decreases and costs increase
Solution Approach 1:
The patent applies preliminary action by pre-modifying the hard mask layer composition (creating silicon-rich oxide) before the etching process begins. This preliminary compositional adjustment prevents micromasking residue formation at the source during etching, eliminating the need for subsequent washing steps or oxygen-deficient layers, thereby maintaining high processing efficiency while achieving defect reduction.
Solution Approach 2:
The patent extracts the problematic stoichiometric oxide component from the hard mask layer and replaces it with silicon-rich oxide material. By removing the problematic component (stoichiometric oxide that forms micromasking residue) and retaining only the beneficial silicon-rich properties, the solution achieves defect reduction without requiring additional processing steps.
3Manufacturing precision
If conventional oxide etching process is used to pattern hard mask layer, then the pattern transfer is achieved, but significant micromasking residue remains at the interface
Solution Approach 1:
The patent changes the chemical parameter of the hard mask layer from stoichiometric oxide to silicon-rich oxide (Si:O ratio > 1:2). This compositional parameter change fundamentally alters the etching behavior at the hard mask/barrier layer interface, enabling effective pattern transfer while simultaneously preventing micromasking residue formation that plagues conventional processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly minimizes micromasking residue, reducing the occurrence of short circuit defects between metal interconnect lines and improving the efficiency of the semiconductor processing without increasing costs.
Implementation Method 1
etching through the interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe
Implementation Method 2
employing a fluorine-containing etch recipe, specifically using CF4 and CHF3, to etch through the interface
Data Source
AI summary
Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.