Etching Prevention Patterns in 3D Semiconductor Stacks
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density and reliability due to the high cost and complexity of forming fine patterns, while three-dimensional semiconductor devices are expensive and have concerns regarding reliable device characteristics.
Innovation Solution
A semiconductor device with a stack structure of alternately stacked insulating and electrode patterns, featuring etching prevention patterns with a lower etch rate than device isolation layers, which are spaced apart by insulating patterns to improve reliability and reduce the diffusion of hydrofluoric acid, thereby enhancing the reliability of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor devices are used to overcome integration density limitations, then integration density is improved, but manufacturing cost and device reliability concerns increase
Solution Approach 1:
The device is divided into distinct functional regions with device isolation layers separating adjacent stack structures. This segmentation prevents harmful interactions between neighboring devices while maintaining the three-dimensional integrated structure, thereby improving reliability without sacrificing integration density.
Solution Approach 2:
Device isolation layers act as intermediary structures between adjacent stack structures. These isolation layers prevent the diffusion of hydrofluoric acid and other harmful substances between neighboring devices, ensuring reliable operation of three-dimensional semiconductor devices while maintaining high integration density.
2Productivity
If fine patterns are formed in conventional two-dimensional semiconductor devices to increase integration density, then integration density is improved, but manufacturing cost increases due to expensive apparatuses
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional stacked structures. By arranging memory cells in the vertical dimension rather than only in the horizontal plane, integration density increases without requiring finer lateral patterning, thereby avoiding the need for expensive fine-pattern forming apparatuses.
3Reliability
If device isolation layers are used to separate stack structures, then device reliability is improved, but hydrofluoric acid diffusion between structures may occur
Solution Approach 1:
The device isolation layers are formed as composite structures with multiple functional layers including etch stop layers and isolation materials. This composite structure provides both mechanical isolation and chemical barrier functions, preventing hydrofluoric acid diffusion while maintaining device reliability.
Solution Approach 2:
Etch stop layers are incorporated within the device isolation structure to preemptively block the diffusion path of hydrofluoric acid. These layers are specifically designed to resist etching by hydrofluoric acid, thereby preventing harmful substance diffusion before it can affect adjacent devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and integration density of semiconductor devices by reducing the etching complexity and cost, while maintaining the structural integrity and performance of three-dimensional semiconductor devices.
Implementation Method 1
an etch rate of the first and second etching prevention patterns by hydrofluoric acid (HF) may be lower than an etch rate of the first and second device isolation layers by hydrofluoric acid (HF)
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.