Etching Stop Films for Semiconductor Devices

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Solution Overview

Problem

The challenge in semiconductor device manufacturing is to ensure reliable and efficient formation of interlayer insulating films between gate structures without voids, while managing the thickness of etching stop films to prevent over-etching and maintain device characteristics.

Innovation Solution

The solution involves forming first and second etching stop films with different thicknesses on NMOS and PMOS regions by diffusing nitrogen and carbon atoms into the semiconductor extension layers and compression stress patterns, respectively, to facilitate the formation of contact holes and interlayer insulating films, thereby controlling the distance between gates and reducing void formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thick etching stop film is formed on the PMOS region to prevent over-etching, then over-etching is prevented, but the contact hole formation becomes difficult and voids may form in interlayer insulating films

Engineering Contradiction:
Improveover-etching preventionVSAvoidcontact hole formation quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies different thicknesses of etching stop films to different regions: a first etching stop film with thickness of 50-150 nm is formed on the NMOS region, while a second etching stop film with thickness of 10-50 nm is formed on the PMOS region. This local differentiation allows the PMOS region to have sufficient etching stop capability while preventing excessive thickness that would cause contact hole formation difficulties and voids.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If the etching stop film thickness is reduced to facilitate contact hole formation, then contact hole formation becomes easier, but over-etching risk increases

Engineering Contradiction:
Improvecontact hole formation qualityVSAvoidover-etching prevention
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent implements region-specific etching stop film thicknesses where the NMOS region receives a thicker first etching stop film (50-150 nm) for robust over-etching prevention, while the PMOS region receives a thinner second etching stop film (10-50 nm) that facilitates contact hole formation and prevents voids. This local quality approach resolves the contradiction by optimizing thickness for each region's specific requirements.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If uniform thickness etching stop films are formed on both NMOS and PMOS regions, then the manufacturing process is simplified, but either over-etching protection or contact hole formation quality cannot be optimized for both regions

Engineering Contradiction:
Improveetching stop film formation processVSAvoiddevice characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs selective thickness control of etching stop films across different device regions. By forming a first etching stop film of 50-150 nm on the NMOS region and a second etching stop film of 10-50 nm on the PMOS region, the patent optimizes each region's performance characteristics while maintaining a relatively simple manufacturing process that forms these differentiated layers in sequence.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the effective formation of interlayer insulating films without voids, improves electrical characteristics, and reduces over-etching risks by controlling the thickness of etching stop films, enhancing the reliability and functionality of semiconductor devices.

Implementation Method 1

forming first and second etching stop films on the NMOS region and the PMOS region, respectively, by diffusing at least one of nitrogen atoms and carbon atoms into the NMOS region and the PMOS region exposed by the gate structure

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9401360B2Semiconductor devices including etching stop films
Publication Date: 2016.07.26 SAMSUNG ELECTRONICS CO LTD
  • US9401360B2 patent drawing
  • US9401360B2 patent drawing
  • US9401360B2 patent drawing

AI summary

A semiconductor device may include a substrate including an NMOS region and a PMOS region. A gate structure can include a gate pattern and a spacer pattern, where the gate structure is on the substrate. A first etching stop film can be on the substrate in the NMOS region and a second etching stop film can be on the substrate in the PMOS region. A contact hole can penetrate the first and second etching stop films and a contact plug can be in the contact hole. A thickness of the first etching stop film can be greater than a thickness of the second etching stop film. Related methods are also disclosed.