Etching Stop Layer Pattern for Semiconductor Memory Parasitic Capacitance
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Solution Overview
Problem
The use of an etching stop layer in semiconductor memory devices increases parasitic capacitance, leading to resistance-capacitance (RC) delay and interference between conductive lines, which is not effectively addressed by existing techniques.
Innovation Solution
The implementation of an etching stop layer pattern that exposes the dielectric layer in non-contact areas and covers it in contact areas, reducing the area of the etching stop layer between conductive lines, thereby minimizing parasitic capacitance and securing overlay margin between conductive lines and contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etching stop layer is used to secure overlay margin between bit line and contact plug, then overlay precision is improved, but parasitic capacitance between bit lines increases
Solution Approach 1:
The etching stop layer is segmented into a patterned structure rather than being continuous. The etching stop layer pattern is formed to have openings at specific locations, allowing it to cover the dielectric layer in some areas while exposing it in others. This segmentation reduces the overall area of the high-dielectric-constant material, thereby reducing parasitic capacitance between bit lines while still providing overlay margin where needed.
Solution Approach 2:
The etching stop layer pattern is strategically positioned to provide local coverage only where overlay margin is critical. By forming the etching stop layer pattern to cover the dielectric layer in contact areas while exposing it in non-contact areas, the solution provides manufacturing precision locally at the contact plug-bit line interface without unnecessarily increasing parasitic capacitance in other regions.
2Object-generated harmful factors
If the area of etching stop layer between conductive lines is reduced, then parasitic capacitance decreases, but overlay margin between conductive line and contact plug may be compromised
Solution Approach 1:
The etching stop layer is divided into a patterned structure with strategic openings. This segmentation allows the layer to maintain coverage in areas where overlay margin is critical (contact areas) while being removed or opened in areas where it would contribute to parasitic capacitance (non-contact areas between conductive lines).
Solution Approach 2:
The etching stop layer pattern is designed with spatially varying properties: it covers the dielectric layer in contact areas to ensure overlay margin, and exposes the dielectric layer in non-contact areas to reduce parasitic capacitance. This local differentiation optimizes both competing requirements.
Data Source
AI summary
A semiconductor memory device of the present invention includes a first dielectric layer located on an upper surface of a semiconductor substrate including contact area and a non-contact area, an etching stop layer pattern formed to expose the first dielectric layer in the non-contact area and cover the first dielectric layer in the contact area, a contact hole extended to the semiconductor substrate of the contact area through the etching stop layer pattern and the first dielectric layer, a contact plug located in the contact hole, and a conductive line connected to the contact plug.