Etching Stopper Layer Layout for High-Voltage Oxide Semiconductor Transistors
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Solution Overview
Problem
Existing semiconductor devices with oxide semiconductor transistors face challenges in maintaining stable transistor characteristics when high voltages are applied to the gate electrode, particularly due to the impact of etching stopper layers on electrical properties and the need for reliable ion implantation processes.
Innovation Solution
The semiconductor device incorporates a thinner etching stopper layer above the channel area, a thicker second insulating layer, and a silicon nitride layer as a gate insulating film to withstand high gate voltages, along with a manufacturing process that includes precise ion implantation through a mask to form low-resistive source and drain areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etching stopper layer is provided on the first insulating layer to control etching depth, then etching precision is improved, but the transistor characteristics become unstable when high voltage is applied to the gate electrode
Solution Approach 1:
The patent applies local quality by making the etching stopper layer thinner specifically in the channel area compared to other regions. This localized thickness variation allows the stopper layer to serve dual purposes: maintaining etching depth control precision while reducing its negative impact on transistor characteristics when high voltage is applied. The channel area has different structural requirements than source/drain regions, and this principle addresses that spatial differentiation.
Solution Approach 2:
The patent changes the thickness parameter of the etching stopper layer based on location. By adjusting the thickness from a uniform value to a variable value (thinner in channel area, thicker elsewhere), the system optimizes both etching control and electrical performance. This parameter modification resolves the contradiction by finding an optimal thickness value that balances mechanical function (etching stop) with electrical function (transistor stability).
2Reliability
If a thicker insulating layer is used to withstand high gate voltages, then reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the insulating structure into multiple functional layers: first insulating layer, etching stopper layer (with variable thickness), and second insulating layer. This segmentation allows each layer to have optimized thickness for its specific function. The second insulating layer can be thicker to handle high voltage, while the etching stopper layer remains thin in critical areas to maintain transistor stability, thus achieving high voltage capability without uniformly increasing all layer thicknesses.
Solution Approach 2:
The patent introduces dimensional variation by making the etching stopper layer's thickness position-dependent (different thickness in channel area vs. other areas). This moves from a one-dimensional uniform thickness approach to a two-dimensional variable thickness approach, enabling simultaneous satisfaction of conflicting requirements: high voltage withstanding in some regions and transistor stability in others.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures stable transistor performance under high gate voltages, enhances reliability, and simplifies the manufacturing process by preventing etching progression and hydrogen/moisture diffusion, thereby maintaining consistent electrical properties.
Implementation Method 1
a silicon nitride layer as a gate insulating film to withstand high gate voltages
Implementation Method 2
a manufacturing process that includes precise ion implantation through a mask to form low-resistive source and drain areas
Implementation Method 3
an etching stopper layer provided on the first insulating layer, located immediately above the channel area
Implementation Method 4
simplifies the manufacturing process by preventing etching progression and hydrogen/moisture diffusion, thereby maintaining consistent electrical properties
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.