Etching Suppressing Portion for Semiconductor Memory Contact Formation

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Solution Overview

Problem

In semiconductor memory devices with a stacked cross-point structure, forming a low-resistance contact between wiring layers is challenging due to excessive etching that can lead to high contact resistance, particularly when forming contact holes that expose both the upper and side faces of the wiring layers.

Innovation Solution

Incorporating an etching suppressing portion above the connection portions of the wiring layers, which slows down the etching process and prevents excessive removal of the wiring layers, allowing for the formation of contact holes that expose both the upper and side faces, thereby enabling a conductive contact layer to connect the wiring and electrode layers effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching is used to form contact holes, then contact holes can be formed to reach the wiring layer, but excessive etching occurs leading to high contact resistance

Engineering Contradiction:
Improvecontact hole formation precisionVSAvoidcontact resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

An etching suppressing portion is formed above the connection portion before the contact hole etching process. This preliminary structure prevents excessive etching by suppressing the etching reaction in the upper region, ensuring the etching stops at the desired depth to expose both upper and side faces of the wiring layer without penetrating too deep and causing high contact resistance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etching suppressing portion is selectively positioned only above the connection portion where contact holes need to be formed. This local modification creates different etching characteristics in different regions: the etching is suppressed above the connection portion to prevent over-etching, while remaining active in other regions to properly form the contact holes

Inventive Principle:
Principle #3Local quality

2Reliability

If etching is suppressed to prevent wiring layer removal, then contact resistance is reduced, but contact hole formation becomes difficult

Engineering Contradiction:
Improvecontact resistanceVSAvoidcontact hole formation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The etching suppressing portion is selectively positioned only above the connection portion, creating localized etching suppression. This allows contact holes to be properly formed in other regions while preventing excessive etching only where needed, thus maintaining both manufacturability and low contact resistance

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The etching suppressing portion is prepared in advance before the contact hole etching process. This preliminary structure ensures that when etching is performed, the contact holes can be formed correctly while the suppressing portion automatically prevents over-etching, simplifying the manufacturing process

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces contact resistance between the wiring and contact layers, improving the electrical connectivity and memory performance by ensuring a stable and efficient contact structure across the semiconductor memory device.

Implementation Method 1

an etching suppressing portion above the connection portions, which slows down the etching process and prevents excessive removal of the wiring layers

Methodology Applied
Scientific EffectEtching suppression:

Data Source

PatentUS8912655B2Semiconductor memory device, method of manufacturing the same and method of forming contact structure
Publication Date: 2014.12.16 KIOXIA CORP
  • US8912655B2 patent drawing
  • US8912655B2 patent drawing
  • US8912655B2 patent drawing

AI summary

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.