Timer Width Correction for Synchronized EtherCAT Control Signals
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Solution Overview
Problem
In EtherCAT systems, synchronization signals and control signals generated by separate processors can lead to timing errors, causing desynchronization among slaves, which disrupt coordinated operations if not corrected.
Innovation Solution
A control device with a first processor acquiring synchronization signals and a second processor generating control signals using a timer, where errors between signal timings are corrected by adjusting the timer width for subsequent periods, ensuring synchronization between synchronization and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronization signal and control signal are generated by separate processors, then processing capability is improved, but timing synchronization deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors the timing difference between the synchronization signal from the first processor and the control signal from the second processor. When a timing error is detected, the system adjusts the timer width in subsequent periods to correct the synchronization error, ensuring that separate processors can operate independently while maintaining precise timing coordination through continuous feedback and adjustment.
2Measurement precision
If timer width is adjusted to correct timing error, then timing synchronization is improved, but system complexity increases
Solution Approach 1:
The patent changes the parameter of timer width dynamically to correct timing synchronization errors. By adjusting this single parameter based on detected timing differences, the system achieves synchronization without introducing complex hardware modifications or additional processing mechanisms, thereby maintaining relatively simple system architecture while improving timing precision.
Data Source
AI summary
A control device includes a first processor that acquires a synchronization signal that is generated every first period, and a second processor that generates a second period that is obtained by dividing the first period by n (n≥1), generates a control signal, using a timer, every third period that is obtained by dividing the second period by m (m≥2), where at least one of a plurality of control signals generated in the first period is a control signal that should be synchronous with the synchronization signal, and in a case where occurrence of an error between timings of the synchronization signal and the control signal that should be synchronous with the synchronization signal is detected, the second processor corrects the error by temporarily changing a width of the timer that is to be started at next and later times.