EtherCAT Wake-Up and Signal Quality Circuit for Low-Power Nodes

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Solution Overview

Problem

EtherCAT networks lack support for low power modes, remote power management, cable diagnostics, and clock daisy-chaining, leading to inefficiencies and lack of mechanisms for node wake-up, signal quality assessment, and effective clock signal configuration.

Innovation Solution

The implementation of an EtherCAT device with a communications circuit, a wakeup circuit, and a clock circuit that enables data transmission, node sleep mode management, wake-on-LAN functionality, and signal quality evaluation, along with clock generation and propagation modes, addresses these shortcomings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If EtherCAT nodes continuously operate in active mode to ensure immediate responsiveness, then network reliability is improved, but energy consumption increases

Engineering Contradiction:
Improvenetwork responsivenessVSAvoidnode power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management by allowing EtherCAT nodes to switch between active and low-power states based on operational needs. The master node can remotely wake up slave nodes from low-power mode, enabling the network to adapt its power consumption dynamically while maintaining the ability to respond to events when needed.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If EtherCAT networks implement remote wake-up functionality for nodes in low-power mode, then energy efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvepower management efficiencyVSAvoidwake-up mechanism complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent reuses the existing Ethernet wake-on-LAN (WoL) packet mechanism for EtherCAT networks, allowing the same packet structure and processing logic to serve both standard Ethernet and EtherCAT protocols. This multi-functional approach enables remote wake-up capability without requiring entirely new signaling mechanisms, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If EtherCAT networks add cable diagnostics and signal quality assessment mechanisms, then network reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesignal quality monitoringVSAvoiddiagnostics circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-diagnostic capabilities where the EtherCAT network automatically assesses signal quality and cable conditions during normal operation. The system uses existing communication channels to exchange diagnostic information between master and slave nodes, enabling the network to self-monitor and report cable diagnostics without requiring separate dedicated diagnostic hardware.

Inventive Principle:
Principle #25Self-service

4Adaptability or versatility

If EtherCAT networks implement clock daisy-chaining configuration, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveclock configuration flexibilityVSAvoidclock circuit configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic clock configuration where slave nodes can be dynamically assigned to different clock modes (daisy-chain, independent, or master-controlled) based on network requirements. The master node can remotely configure the clock operating mode of slave nodes, allowing the network to adapt its clock distribution architecture dynamically without requiring complex hardwired configurations for each possible topology.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12047480B2EtherCAT device
Publication Date: 2024.07.23 MICROCHIP TECHNOLOGY INC
  • US12047480B2 patent drawing
  • US12047480B2 patent drawing
  • US12047480B2 patent drawing

AI summary

An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.