Ethernet Data Distribution Using Dynamic Multi-Circuit Bandwidth Scaling
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Solution Overview
Problem
Current Ethernet interface designs require multiple types of physical subboards and chips due to different bandwidth rates, leading to a heavy workload and increased costs, as existing fixed-rate single-port Ethernet interfaces struggle to meet complex bandwidth configuration requirements.
Innovation Solution
A data distribution method that processes packet streams into data block streams, which are then distributed to multiple second circuits in a physical layer circuit, allowing for flexible bandwidth configuration by enabling or disabling circuits based on the packet stream rate, and performing physical layer encoding, scrambling, and alignment marker insertion or removal as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple types of physical subboards and Ethernet interface chips are designed for different bandwidth rates, then different bandwidth requirements can be met, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent implements a universal physical subboard design where a single type of subboard can support multiple bandwidth rates (10G, 25G, 40G, 100G) through software configuration and dynamic circuit activation. The subboard includes multiple circuits that can be selectively enabled or disabled based on the required bandwidth, eliminating the need for multiple dedicated subboard types for different rates.
Solution Approach 2:
The patent introduces dynamic bandwidth adjustment capability where the operational bandwidth of the Ethernet interface can be changed in real-time by activating or deactivating specific circuits through software control. This dynamic reconfiguration allows the same hardware to adapt to different bandwidth requirements without physical changes or reconfiguration of the hardware architecture.
2Adaptability or versatility
If multiple types of Ethernet interface chips are designed for different bandwidth rates, then various bandwidth modes can be supported, but workload and development cost increase
Solution Approach 1:
The patent designs a universal Ethernet interface chip that can operate at multiple bandwidth rates (10G, 25G, 40G, 100G) through a single chip design. The chip includes multiple circuits that can be selectively activated based on the required bandwidth mode, allowing one chip to replace what would traditionally require multiple different chip designs for different rates.
Solution Approach 2:
The patent changes the operational parameters of the Ethernet interface by dynamically adjusting which circuits are active based on the required bandwidth rate. Instead of designing different chips with fixed parameters for different rates, the system uses parameter changes (circuit activation states) to achieve different bandwidth modes from the same chip design.
3Device complexity
If fixed-rate single-port Ethernet interfaces are used, then implementation is simplified, but complex bandwidth configuration requirements cannot be met
Solution Approach 1:
The patent transforms the fixed-rate interface into a dynamic interface that can adjust its bandwidth rate based on configuration requirements. The system includes control logic that can activate or deactivate specific circuits to achieve different bandwidth rates (10G, 25G, 40G, 100G), maintaining implementation simplicity while gaining configurability.
Solution Approach 2:
The patent segments the Ethernet interface into multiple independent circuits that can be selectively activated. Each circuit corresponds to a specific bandwidth rate, and the system can enable or disable individual circuits based on the required bandwidth configuration, allowing flexible rate adjustment while keeping the overall implementation relatively simple.
Data Source
AI summary
A data distribution method, a data aggregation method, and related apparatuses are disclosed. The data distribution method may include: receiving a first packet stream; dividing the first packet stream to obtain a first data block stream; sending the first data block stream to a first circuit; processing, by the first circuit, the first data block stream to obtain a first data stream; distributing, by the first circuit, the first data stream to N1 second circuits of M second circuits in a PT-W, where M is greater than N1, N1 is a positive integer, and M is a positive integer; and processing, by the N1 second circuits, the received first data stream to obtain N1 first code streams. The technical solutions provided by the embodiments of the present application help to meet a requirement for complex bandwidth configuration and extend an application scenario.