Ethernet Interface Clock Harmonization for Low-EME Networking

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Solution Overview

Problem

In Ethernet-based networks, point-to-point topologies require more wires and are costly, while multi-drop topologies face physical constraints, and existing media access control methods may incorrectly handle collisions, leading to inefficiencies and interference.

Innovation Solution

Implementing a process that generates a clock for an Ethernet physical layer at a first rate and couples it with a link layer using a second clock rate equal to or less than the bit rate, with a harmonizing sublayer to synchronize bit and clock rates, reducing electromagnetic emissions and improving collision handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If point-to-point topology is used, then network performance and reliability are improved, but the number of wires and cost increase

Engineering Contradiction:
Improvenetwork reliabilityVSAvoidnumber of wires
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple data lanes into a single differential pair using parallel transmission techniques. Multiple data streams are transmitted simultaneously over shared physical medium, reducing the total number of wires required while maintaining point-to-point reliability through logical channel separation and error handling mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent enables a single physical connection to serve multiple communication functions by implementing multi-lane serialization/deserialization. The same physical interface can dynamically allocate bandwidth to different data streams, making the connection universally applicable to various network requirements without requiring dedicated wires for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If multi-drop topology is used, then wire quantity is reduced, but physical constraints and interference increase

Engineering Contradiction:
Improvenumber of wiresVSAvoidelectromagnetic interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent segments the shared physical medium into multiple isolated logical channels using differential signaling and encoding schemes. Each data stream is treated as a separate channel with its own timing and error handling, effectively dividing the multi-drop environment into multiple virtual point-to-point connections that resist electromagnetic interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a physical layer device as an intermediary between multiple network devices on a shared medium. This intermediary handles signal regeneration, timing synchronization, and collision management, isolating devices from direct electromagnetic interference while maintaining efficient multi-device communication over reduced wiring.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If baseband transmission is used, then simplicity is improved, but electromagnetic emissions increase

Engineering Contradiction:
Improvetransmission simplicityVSAvoidelectromagnetic emissions
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent employs periodic clocking and synchronized transmission intervals to control electromagnetic emissions. By organizing data transmission into regular time slots with controlled rise and fall times of signal edges, the system maintains simple baseband operation while reducing spectral spreading and electromagnetic radiation through disciplined periodic signaling.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11171732B2Ethernet interface and related systems methods and devices
Publication Date: 2021.11.09 MICROCHIP TECHNOLOGY INC
  • US11171732B2 patent drawing
  • US11171732B2 patent drawing
  • US11171732B2 patent drawing

AI summary

Described is a digital interface and related systems, method and devices. In some embodiments an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.