Ethernet Clock Synchronization via Overlay Timeslots
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Solution Overview
Problem
Ethernet networks face challenges in providing sufficient Quality of Service (QoS) for time division multiplexed (TDM) data due to jitter and data loss issues, which are not adequately addressed by existing enhancements, limiting its implementation in TDM networks like PSTN.
Innovation Solution
The implementation of Huawei-Enhanced (HE) Ethernet operational modes, including frequency-synchronized communication mode (H-Sync) and frequency-synchronized and phase-aligned communication mode (H-TDM), which utilize timestamps in inter-packet gaps and overlay synchronous timeslots to ensure deterministic data transfer and synchronize clocks between nodes, supporting stringent QoS requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ethernet packets are transported through the network with resource arbitration and buffers at nodes, then data loss is reduced, but network complexity increases
Solution Approach 1:
The patent extracts TDM traffic from standard Ethernet sharing and places it in dedicated overlay synchronous timeslots. This separation removes TDM packets from contention with other traffic, eliminating the need for complex resource arbitration and buffering mechanisms while maintaining deterministic delivery.
Solution Approach 2:
The patent segments Ethernet traffic into standard data packets and TDM packets, with TDM packets transmitted in dedicated overlay timeslots. This segmentation isolates TDM traffic from general Ethernet contention, reducing complexity for time-sensitive data transport.
2Reliability
If resource arbitration and prioritization are implemented, then QoS is improved, but delay increases
Solution Approach 1:
The patent pre-allocates specific overlay synchronous timeslots for TDM traffic transmission. This preliminary assignment of dedicated time slots eliminates the need for real-time resource arbitration, providing deterministic low-delay transmission for TDM packets without requiring complex scheduling decisions during data transfer.
3Reliability
If existing Ethernet enhancements are implemented, then jitter issues are partially addressed, but coupling with TDM QoS requirements is insufficient
Solution Approach 1:
The patent creates a universal solution by overlaying synchronous timeslots that can carry TDM traffic while maintaining compatibility with standard Ethernet infrastructure. This multi-functional approach allows existing Ethernet networks to support TDM QoS requirements without requiring complete protocol replacement, achieving both jitter reduction and proper QoS coupling.
Solution Approach 2:
The patent introduces overlay synchronous timeslots as an intermediary layer between standard Ethernet and TDM requirements. This intermediary mechanism provides the deterministic timing and QoS guarantees needed for TDM traffic while operating within the existing Ethernet framework, bridging the gap between the two systems.
Data Source
AI summary
A network component comprising a processor configured to implement a method comprising promoting transmission of a first frame comprising a first timestamp associated with a transmission time of the first frame, recognizing a reception of a second frame having a reception time, wherein the second frame comprises a second timestamp comprising a downstream node delay associated with a downstream node, measuring a total delay between the transmission time of the first frame and the reception time of the second frame, and calculating a transport delay using the total delay and the downstream node delay. Also disclosed is a clock synchronization method comprising receiving a first frame comprising a first timestamp associated with an upstream clock at a reception time, sending a second frame at a transmission time, and measuring a downstream node delay between the reception time and the transmission time, wherein the second frame comprises the downstream node delay.