Multiport Ethernet Clock Synchronization via Phase-Locked Loop
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Solution Overview
Problem
Multi-segment Ethernet links often violate clock synchronization requirements between mobile base stations and center nodes due to different clock frequency references across each link segment, which is not effectively addressed by existing technologies.
Innovation Solution
The implementation of dual-port nodes with phase-locked loops (PLLs) and programmable control logic within multiport devices, where slave ports synchronize with master ports using a reference clock, and a processing module with a smoothing filter to adjust frequencies and maintain synchronization across multiple segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If multiple Ethernet link segments are used to extend range, then the communication distance is improved, but clock synchronization between nodes deteriorates due to different clock frequency references
Solution Approach 1:
The patent introduces a dual-port node as an intermediary device between master and slave ports. This intermediary contains a phase-locked loop (PLL) that receives clock signals from both ports and generates synchronized output, acting as a mediator to reconcile the different clock frequency references across multiple Ethernet segments while maintaining extended communication range
Solution Approach 2:
The patent implements feedback mechanisms where the dual-port node continuously monitors clock signals from both master and slave ports, compares their frequencies, and adjusts the PLL output accordingly. This feedback loop ensures that clock synchronization is maintained across all segments, preventing drift and maintaining timing accuracy over extended distances
2Reliability
If dual-port nodes with PLLs are added to synchronize clocks, then clock synchronization is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock synchronization function with the existing Ethernet port functionality by integrating the dual-port node design into standard Ethernet switches and routers. The PLL and control logic are combined with the port controller, allowing clock synchronization to be achieved without adding separate dedicated hardware, thus reducing overall device complexity
Solution Approach 2:
The dual-port node serves multiple functions: it acts as a standard Ethernet port for data communication, a clock recovery point for synchronization, and a frequency adjustment stage through the PLL. This multi-functionality eliminates the need for separate synchronization devices, reducing system complexity while maintaining reliable clock synchronization across extended Ethernet segments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures tight clock synchronization across multiple Ethernet link segments, reducing clock signal jitter and maintaining frequency consistency, thereby addressing the synchronization challenges in multi-segment Ethernet links.
Implementation Method 1
The implementation of dual-port nodes with phase-locked loops (PLLs) and programmable control logic within multiport devices, where slave ports synchronize with master ports using a reference clock
Data Source
AI summary
A method for frequency synchronization of a multiport device may include recovering a clock frequency of a master port of a first device that is linked to the multiport device at a slave port of the multiport device. A clock frequency of the slave port may be locked to the recovered-clock frequency of the master port of the first device. Frequency data may be stored in a first frequency register associated with the slave port. The stored frequency data may include a difference between the recovered-clock frequency of the master port of the first device and a local-clock frequency of the multiport device. A clock frequency of one or more master ports of the multiport device may be synchronized with the locked clock frequency of the slave port by coupling the first frequency register to frequency registers associated with one or more master ports.