Ethernet Controller SERDES Lane Bonding for 50 Gb/s

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Solution Overview

Problem

Current Ethernet networks in blade servers face limitations in achieving high data rates, particularly in scalable server infrastructures for enterprise or cloud computing, as they often operate at speeds lower than required for efficient data transmission across multiple nodes without significant increases in cost or complexity.

Innovation Solution

The implementation of an Ethernet controller that distributes Ethernet frames across multiple serializer/deserializer (SERDES) lanes, enabling data rates of up to 50 Gb/s by bonding multiple lanes together, thereby overcoming the speed limitations of traditional Ethernet ports operating at 10 Gb/s or 20 Gb/s, and allowing for efficient data transmission across blade server midplanes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional Ethernet ports operating at 10 Gb/s or 20 Gb/s are used, then device complexity is kept simple, but data transmission speed is insufficient for efficient data transmission across multiple nodes

Engineering Contradiction:
Improvedata transmission speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the high-speed data transmission task across multiple SERDES lanes, where each lane operates at a manageable speed (e.g., 10 Gb/s or 20 Gb/s) but collectively they achieve the desired high throughput (50 Gb/s or 100 Gb/s). This segmentation allows the system to achieve high speed without requiring each individual component to operate at extremely high speeds, thereby managing device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple SERDES lanes into a single logical high-speed interface. By merging the capacity of multiple lanes through techniques like lane bonding or aggregation, the system achieves high data transmission speeds while using standard, lower-speed SERDES components, thus avoiding the need for complex high-speed interface hardware.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If multiple SERDES lanes are bonded together to achieve 50 Gb/s, then data transmission speed increases, but device complexity increases

Engineering Contradiction:
Improvedata transmission speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent makes existing SERDES infrastructure multi-functional by enabling it to operate in both standalone mode (for lower-speed applications) and bonded mode (for high-speed applications). This universality allows the same physical lanes to serve different purposes based on configuration, reducing the need for dedicated high-speed hardware and minimizing additional device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces intermediary components such as lane bonding logic, multiplexers, or switch fabric that mediate between multiple SERDES lanes and the external interface. These intermediaries manage the complexity of coordinating multiple lanes by providing standardized interfaces and control mechanisms, thereby shielding higher-level protocols from the underlying complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If existing infrastructure is utilized to support 50 Gb/s Ethernet traffic, then cost per server is controlled, but achieving high data rates becomes challenging

Engineering Contradiction:
Improvecost per serverVSAvoiddata transmission speed
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent implements dynamic lane bonding where the number and configuration of active SERDES lanes can be adjusted based on traffic requirements. This dynamic capability allows the system to optimize performance for different workloads using the same physical infrastructure, achieving high data rates when needed while maintaining cost-effectiveness by not permanently provisioning dedicated high-speed resources for all scenarios.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9438536B250 Gb/s Ethernet using serializer/deserializer lanes
Publication Date: 2016.09.06 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9438536B2 patent drawing
  • US9438536B2 patent drawing
  • US9438536B2 patent drawing

AI summary

Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.