Ethernet Hardware Verification Using CRC Correction Lookup

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Solution Overview

Problem

The verification of Ethernet hardware performance is hindered by the complexity of recalculating checksum and CRC values, especially when timestamping is involved, due to the need for precise timing and the challenge of processing large data frames efficiently within a single clock cycle.

Innovation Solution

A system that efficiently determines a modified checksum and CRC value by nullifying the checksum in the data frame, incorporating a timestamp, and combining it with a CRC correction value, allowing for processing in a single hardware clock cycle with minimal additional logic, thus maintaining performance and reducing area usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If checksum and CRC values are recalculated with timestamping in Ethernet hardware verification, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvetiming verification accuracyVSAvoidverification logic complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores CRC correction values for all possible checksum values before the verification process. During timestamping operations, the system simply retrieves the pre-computed correction value corresponding to the new checksum, avoiding complex real-time CRC recalculations. This preliminary preparation reduces the complexity of the verification logic while maintaining precise timing measurements.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a CRC correction value as an intermediary element that mediates between the checksum calculation and the final CRC verification. Instead of directly recalculating the entire CRC when timestamping occurs, the system computes a correction value that adjusts the original CRC to account for the timestamp modification. This intermediary approach simplifies the verification logic while preserving measurement accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If checksum and CRC recalculations are performed for timestamped packets, then reliability is improved, but productivity decreases

Engineering Contradiction:
Improveverification correctnessVSAvoidpacket processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system pre-computes and stores a lookup table of CRC correction values corresponding to all possible checksum values. During packet timestamping, instead of performing complex real-time CRC recalculations that would reduce throughput, the system quickly retrieves the appropriate correction value from the pre-computed table and applies it to the existing CRC. This maintains verification reliability while preserving high packet processing productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent transforms the verification process by changing from direct CRC recalculation to CRC correction using pre-computed values. This parameter change in the verification approach maintains the reliability of checksum and CRC verification while significantly improving processing speed and throughput during timestamping operations.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If additional logic is added for checksum and CRC correction, then measurement precision is improved, but area usage increases

Engineering Contradiction:
Improvetimestamp verification accuracyVSAvoidhardware area usage
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent pre-calculates and stores CRC correction values in a compact lookup table structure during the design phase. The hardware implementation uses this pre-computed data to perform verification with minimal additional logic during operation. This approach achieves precise timestamp verification while minimizing the area usage during the actual verification process, as the complex computation is performed offline rather than in the critical hardware path.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a compact representation and storage method for the CRC correction values, effectively creating an optimized copy of the correction data that can be stored in minimal hardware resources. This allows the system to maintain precise verification capabilities without proportionally increasing the hardware area, as the correction data is stored in an space-efficient manner.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11979232B2Verification of Ethernet hardware based on checksum correction with cyclic redundancy check
Publication Date: 2024.05.07 SYNOPSYS INC
  • US11979232B2 patent drawing
  • US11979232B2 patent drawing
  • US11979232B2 patent drawing

AI summary

A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.