Ethernet Data Caching System with Bank Interleaving for 40G and 100G Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data caching systems for high-speed Ethernet devices face challenges such as poor expandability, limited capacity, and low bandwidth utilization due to the limitations of SRAM and SDRAM, particularly at 40G or 100G speeds, where SRAM capacity is insufficient and SDRAM's high power consumption and overheads lead to performance bottlenecks.
Innovation Solution
A data caching system and method that includes an input package process device, package address management, memory control, and output package process device, which convert data frames to uniform bit width and format, manage cache addresses through interleaving, and execute read/write operations efficiently, optimizing cache utilization and expandability by using a combination of SRAM and SDRAM with Bank interleaving and ROUND-ROBIN polling algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used as cache in network switching device, then packet switching speed is improved, but storage capacity becomes insufficient for 40G/100G Ethernet
Solution Approach 1:
The patent divides the cache system into multiple independent cache banks (first cache bank, second cache bank, third cache bank, fourth cache bank) that can be accessed in parallel. This segmentation allows the system to achieve both high switching speed (through parallel access) and large storage capacity (through aggregated bank size), resolving the contradiction between speed and capacity for 40G/100G Ethernet applications.
Solution Approach 2:
The patent employs a composite cache architecture combining multiple SRAM cache banks with different characteristics. By compositeing these cache banks with unified address management and interleaved access, the system achieves both the high speed of SRAM and the large capacity needed for high-bandwidth Ethernet switching.
2Quantity of substance
If SDRAM is used as cache in network switching device, then storage capacity is improved, but bandwidth utilization rate deteriorates due to periodic refreshing and overheads
Solution Approach 1:
The patent segments the SDRAM cache into multiple independent banks that can be accessed in parallel. This allows the system to hide the periodic refreshing overhead of SDRAM by simultaneously accessing different banks, thereby maintaining high bandwidth utilization rate while providing large storage capacity for traffic management.
Solution Approach 2:
Through unified address management and interleaved access across multiple SDRAM banks, the patent ensures continuous useful action by eliminating idle periods caused by SDRAM refreshing overhead. The system maintains continuous data flow and high bandwidth utilization despite the inherent periodic refreshing requirements of SDRAM.
3Device complexity
If conventional caching scheme is used, then device simplicity is maintained, but expandability deteriorates when Ethernet interface bit width is expanded
Solution Approach 1:
The patent implements a universal cache address management device that can manage multiple cache banks with unified addressing. This universal management approach allows the same cache structure to support different Ethernet interface bit widths (from 64-bit XGMII to 640-bit CGMII) and different cache configurations, providing both simplicity and expandability.
Solution Approach 2:
The patent employs dynamic address management that can adapt to different Ethernet interface configurations. The unified address management device dynamically allocates and manages cache addresses across multiple banks, allowing the system to expand from 40G to 100G Ethernet while maintaining a relatively simple base architecture.
4Productivity
If cache address management is optimized with interleaving, then bandwidth utilization is improved, but device complexity increases
Solution Approach 1:
The patent merges the address management functions for multiple cache banks into a single unified address management device. This unified management approach simplifies the overall device architecture while implementing interleaved access patterns that optimize bandwidth utilization, balancing complexity and performance.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A data caching method for an Ethernet device is provided. The method includes: receiving data frames from various Ethernet interfaces and converting the Ethernet data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; maintaining a cache address in which data has already been written and a currently idle cache address in a cache; receiving the currently idle cache address and generating a write instruction and/or a read instruction for the cache and performing a write operation and/or a read operation so as to write the data received and processed by an IPC into the currently idle cache or to read data from the cache; and performing bit conversion and format encapsulation on the data that is read according to a read request and outputting the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface. A data caching system for an Ethernet device is also provided. By means of the data caching method and system provided herein, the expandability and the high bandwidth storage capacity of a network switching device can be improved, a high bandwidth utilization rate is achieved, and it becomes possible to improve bandwidth utilization rate based on traffic management.