Concatenated Ethernet FEC Coding for 800G Bit Error Control
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Solution Overview
Problem
The rapid increase in network service throughput and bandwidth in Ethernet protocols, such as IEEE802.3 Ethernet, leads to higher transmission bit errors, particularly with the introduction of next-generation Ethernet 800G, which requires more effective error correction methods.
Innovation Solution
An Ethernet coding method that employs a concatenated coding scheme using two Forward Error Correction (FEC) codewords, specifically a Reed-Solomon (RS) codeword as the outer code and an inner-FEC codeword, to enhance error correction performance and adapt to higher bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a higher transmission bandwidth is used in Ethernet 800G, then the transmission throughput is improved, but the transmission bit error rate increases
Solution Approach 1:
The patent divides the error correction function into two separate FEC codewords: an outer RS-FEC codeword and an inner FEC codeword. This segmentation allows each codeword to specialize in different error correction aspects, with the outer code handling burst errors and the inner code handling random bit errors, thereby achieving better overall error correction performance at 800G bandwidth while maintaining reliability
Solution Approach 2:
The patent employs a composite coding structure by concatenating two different FEC codes (RS-FEC and inner-FEC) with different error correction characteristics. This composite approach combines the strengths of both codes to achieve superior error correction performance compared to using a single code, enabling reliable 800G transmission
2Reliability
If a single FEC codeword is used, then the device complexity is low, but the error correction performance is insufficient for 800G
Solution Approach 1:
The patent segments the error correction task into two distinct FEC codewords with specific functions: the outer RS-FEC codeword for burst error correction and the inner FEC codeword for random error correction. This segmentation enables each component to be optimized independently while achieving superior overall error correction performance suitable for 800G
Solution Approach 2:
The patent optimizes the parameters of the concatenated FEC scheme by carefully selecting the code lengths and information bit lengths of both outer and inner codewords to satisfy specific throughput requirements (M1 and M2) while achieving the necessary error correction performance for 800G Ethernet
Data Source
AI summary
This application discloses an Ethernet coding method and apparatus, to adapt to a scenario in which a higher transmission bit error rate is caused by a high bandwidth. The method includes: a transmit end encodes first to-be-encoded information by using a first forward error correction (FEC) codeword, to obtain first encoded data, where the first forward error correction FEC codeword is a Reed-Solomon forward error correction (RS-FEC) codeword; and the transmit end encodes the first encoded data by using a second FEC codeword, to obtain second encoded data, where a code length N and an information bit length K of the second FEC codeword satisfy the following formula:M1*NK≤M2,where M1 is a throughput of the first encoded data, and M2 is a throughput of the second encoded data.