Ethernet FEC Coding Segmentation for Flexible Gain and Low Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing FEC processing scheme for 40G and 100G Ethernet is inadequate for beyond-100G Ethernet, as it cannot provide varying coding gains and introduces excessive latency, which are essential for meeting the increased bandwidth demands of emerging services like IP video and cloud computing.
Innovation Solution
The proposed Ethernet data processing method involves performing line coding on data from the media access control layer to obtain serial data code blocks, followed by FEC coding that inserts check bits every X consecutive data bits, and distributing these FEC frames at a specific granularity to N virtual channels, allowing for flexible coding gains and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the existing FEC processing scheme based on the physical-layer architecture is used, then the FEC function can be provided, but the maximum coding gain is limited to 2 dB and latency is 430 ns which is too large
Solution Approach 1:
The patent segments the FEC processing by separating the coding function from the physical-layer architecture. The coding gain adjustment is achieved by modifying the code rate parameter in the FEC encoding process, allowing flexible adjustment of coding gain (e.g., 3 dB, 4.5 dB, 6 dB) without being constrained by the fixed physical-layer structure. This segmentation enables independent optimization of coding gain and latency parameters.
Solution Approach 2:
The patent introduces dynamic adjustment capability for coding gain through configurable code rate parameters. The system can dynamically select different coding gain levels based on channel conditions and service requirements, rather than being fixed at 2 dB. This dynamic parameter adjustment resolves the contradiction by allowing the system to optimize between coding gain and latency according to actual needs.
2Reliability
If the existing FEC processing scheme is used, then error-free transmission can be achieved, but the latency introduced is 430 ns which cannot meet the latency requirement of beyond-100G Ethernet
Solution Approach 1:
The patent segments the error correction function from the physical-layer processing chain. By implementing FEC as a separate coding layer with configurable parameters, the system can provide error-free transmission while reducing latency. The segmentation allows the FEC processing to be optimized independently from the physical-layer constraints that caused the 430 ns latency.
Solution Approach 2:
The patent changes key parameters of the FEC processing, particularly the code rate and processing granularity. By adjusting these parameters, the system achieves error-free transmission with reduced latency suitable for beyond-100G Ethernet, breaking away from the fixed parameter set in existing schemes that resulted in 430 ns latency.
3Adaptability or versatility
If the existing FEC processing scheme is used, then a fixed coding gain of 2 dB can be provided, but it cannot provide different coding gains according to different requirements
Solution Approach 1:
The patent introduces dynamic configurability for coding gain through adjustable code rate parameters. The system can adaptively select different coding gain levels (3 dB, 4.5 dB, 6 dB, etc.) based on channel conditions, service types, and quality requirements. This dynamic adaptation resolves the contradiction between providing fixed 2 dB coding gain and enabling flexible coding gain selection.
Solution Approach 2:
The patent enables parameter changes in the FEC coding process, specifically the code rate parameter that directly controls coding gain. By allowing these parameters to be configured and adjusted, the system provides adaptable coding gain suitable for different application scenarios while maintaining reliable error correction performance.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
Embodiments of the present invention disclose an Ethernet data processing method, an Ethernet physical layer chip, and Ethernet equipment. Applicable to data processing at a transmit end, the method includes: performing line coding on data from a media access control layer, so as to obtain serial data code blocks; performing forward error correction FEC coding on the serial data code blocks, so as to obtain FEC frames, which specifically includes: inserting Y check bits every X consecutive data bits, where the Y check bits are generated when FEC coding is performed on the X consecutive data bits; and distributing, at a distribution granularity of a bits, the FEC frames successively to N virtual channels, where a and N are both positive integers, and a is less than a quantity of bits included in one FEC frame. The method, the Ethernet physical layer chip, and the Ethernet equipment provided by the embodiments of the present invention may provide different FEC coding gains according to different requirements, and latency introduced due to FEC processing is very small.