Ethernet FEC Marker Clock Synchronization
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Solution Overview
Problem
Current synchronization methods for high-speed Ethernet link communications, such as PTP and JESD204, face challenges in achieving precise timing synchronization while minimizing clock synchronization errors and reducing complexity and cost in Radio Access Networks (RANs), especially with the introduction of 5G technology and millimeter wavelengths.
Innovation Solution
The method involves using forward error correction (FEC) coding to transmit a FEC marker with a planned transmission time indication, allowing secondary devices to adjust their internal clocks based on the reception time of the FEC marker, thereby calculating a round trip delay and synchronizing with the primary device's clock, reducing the need for additional synchronization signals and processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PTP and radio interface-based methods are used for synchronization, then timing accuracy is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent combines synchronization functionality with existing FEC marker transmission in Ethernet communications. Instead of implementing separate PTP stacks or dedicated synchronization signals, the synchronization information is merged into the FEC marker structure, allowing both error correction and time synchronization to be achieved through a unified mechanism, thereby reducing device complexity while maintaining timing accuracy
Solution Approach 2:
The FEC marker is given multiple functions: it serves both as an error correction component and as a synchronization carrier. By making the FEC marker universal for both purposes, the patent eliminates the need for separate synchronization infrastructure, reducing processing overhead while preserving timing precision requirements
2Measurement precision
If multiple PTP stacks and complex clocking circuitry are implemented, then synchronization accuracy is improved, but computational resources and cost increase
Solution Approach 1:
The system uses existing Ethernet FEC infrastructure to provide synchronization services without requiring additional dedicated synchronization hardware or software stacks. The FEC markers that are already being transmitted for error correction are repurposed to carry synchronization information, allowing the system to serve itself for synchronization needs without external specialized components, thereby reducing computational resource consumption
Solution Approach 2:
The patent extracts the synchronization function from complex PTP implementations and isolates it into simple timestamp comparisons based on FEC marker reception. By separating the essential synchronization requirement from the complex PTP protocol overhead, the system achieves synchronization accuracy without requiring multiple PTP stacks or complex clocking circuitry, thus reducing computational resource usage
Data Source
AI summary
A disclosed method is performed by a primary device that is configured to code data using forward error correction (FEC) coding for transmission to a secondary device. The FEC coding adds a FEC marker to FEC coded data. The method by the primary device includes transmitting to the secondary device a marker planned transmission time indication which indicates when the primary device will transmit the FEC marker toward the secondary device. The method also includes transmitting the FEC marker of the FEC coded data at the time indicated by the marker planned transmission time indication.