Ethernet Fg-BU Frame Lock Detection Using Consecutive Frame Checks

The patent applies preliminary action by pre-defining specific judgment conditions for locking and unlocking states before actual frame processing occurs. The receiving end is configured with predetermined criteria (such as specific bit patterns, frame structure requirements, or synchronization sequence conditions) that must be met to determine locking state. This allows the system to automatically transition between states based on pre-established rules, reducing the complexity of real-time decision-making while maintaining flexible service access capabilities.

The patent merges the MFI functionality with existing frame structure elements by integrating the serial number indication directly into the frame header or synchronization sequences that are already part of the Fg-BU structure. Instead of adding separate MFI fields that would require independent processing, the frame identification information is combined with structural elements that must be processed anyway, thereby improving frame identification accuracy without proportionally increasing processing time.

The patent applies partial action by implementing selective frame checking rather than examining every single frame. The system checks specific frames based on predetermined conditions (such as every Nth frame, or only frames containing specific markers or structure elements), which provides sufficient reliability for locking/unlocking judgment while significantly reducing processing overhead compared to checking every frame. This partial checking approach maintains adequate reliability without sacrificing excessive productivity.