Ethernet Frame Latency Reduction via Intact Block Processing
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Solution Overview
Problem
Conventional Ethernet processing methods incur high latency due to the need for combinatorial logic and timing constraints, which are exacerbated by increasing data path width or clock frequency, making it difficult for high-frequency trading platforms to react quickly to market changes.
Innovation Solution
Processing Ethernet blocks in their intact form, retaining synchronization bits, and transmitting them on a data path that is an integer multiple of the block size, such as 66/n bits, reduces resource requirements and timing constraints, allowing for reduced latency by using control signals to mark block locations and avoid realignment delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data path width or clock frequency is increased to reduce latency, then processing speed is improved, but device complexity and timing constraints worsen
Solution Approach 1:
The patent combines the synchronization bits with the data payload into a unified 66-bit block structure, eliminating the need for separate synchronization handling logic. This merging reduces device complexity while maintaining processing speed, as the synchronized blocks can be processed directly without additional realignment operations that would increase latency.
Solution Approach 2:
The patent segments the Ethernet data stream into fixed 66-bit blocks containing 64 data bits and 2 synchronization bits. This segmentation creates uniformly structured data units that can be processed in parallel with predictable timing, reducing latency without requiring increased clock frequency or data path width, thereby avoiding increased device complexity.
2Productivity
If combinatorial logic is added to process Ethernet blocks, then data processing capability is improved, but latency increases
Solution Approach 1:
The patent performs synchronization bit insertion as a preliminary action during the block formation stage, before the data enters the main processing pipeline. This preliminary structuring eliminates the need for complex realignment logic downstream, reducing both the combinatorial logic required and the processing latency, while maintaining high data processing capability.
3Productivity
If synchronization bits are removed and data is realigned, then data path efficiency is improved, but additional realignment delays increase latency
Solution Approach 1:
Instead of removing synchronization bits and then realigning data (the conventional approach), the patent inverts the approach by retaining the synchronization bits within the 66-bit block structure and using them to maintain alignment information throughout processing. This inversion eliminates realignment delays while preserving data path efficiency, as the synchronization bits continuously provide alignment reference without requiring data extraction or reinsertion operations.
Data Source
AI summary
A bitstream representing an Ethernet frame is received over a physical medium. Encoded Ethernet blocks are recovered from the bitstream. The Ethernet blocks are descrambled and provided to downstream switching logic, intact, without removing the synchronization bits that were added during the encoding process. More particularly, the intact descrambled Ethernet block is divided into smaller-sized data words; the size of the data words being an integer multiple of the size of the Ethernet block.