Hardware Ethernet IP Filter CAM Line Rate Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DOCSIS devices face challenges in efficiently filtering and routing Ethernet packets at line rate due to the computationally intensive nature of IP filtering, which can lead to packet delays and increased processing loads on processors.
Innovation Solution
Implementing a hardware-based downstream IP filter that utilizes a content-addressable memory (CAM) to parse and filter Ethernet frames at line rate, reducing processor involvement and enabling rapid filtering and routing without excessive delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor executes software to parse and filter Ethernet packets, then filtering functionality is achieved, but processing speed decreases and packet delays increase
Solution Approach 1:
The patent replaces the software-based processing mechanism with a hardware-based Content-Addressable Memory (CAM) system. The CAM hardware circuitry directly compares packet headers against filter criteria in parallel, eliminating the sequential software execution bottleneck and achieving line-rate filtering without processor intervention.
Solution Approach 2:
The patent extracts the packet filtering function from the general-purpose processor and implements it as a dedicated hardware CAM filter. This separation allows the processor to focus on higher-level tasks while the CAM hardware handles time-critical packet filtering independently at line rate.
2Reliability
If a processor performs IP filtering, then filtering accuracy is maintained, but processor load increases significantly
Solution Approach 1:
The patent substitutes the processor's software-based filtering with a dedicated CAM hardware system that maintains filtering accuracy through parallel comparison of packet headers against stored filter criteria, while dramatically reducing processor load by offloading the time-critical filtering operations.
Solution Approach 2:
The patent extracts the IP filtering function from the processor and implements it as a standalone hardware CAM filter, allowing the processor to be freed from filtering responsibilities while maintaining comprehensive filtering capabilities through the hardware system.
3Device complexity
If hardware circuitry is shared for upstream and downstream IP filters, then system size and cost are reduced, but hardware resource constraints are imposed
Solution Approach 1:
The patent implements a universal CAM hardware filter design that can operate in both upstream and downstream directions. The same basic CAM architecture, parser, and routing logic are reused for both filter directions, enabling the system to maintain full filtering capacity while reducing overall hardware footprint through resource sharing.
Data Source
AI summary
A filter in a DOCSIS bridge performs IP Filtering of incoming Ethernet packets in hardware. The filter includes a parser circuit which, in hardware, parses each of the incoming Ethernet packets and then utilizes the parsed information in combination with a content-addressable memory (CAM) that stores filtering information, to filter and route the incoming Ethernet packets. Detailed statistical data may also be generated to provide information on the type of filtering being performed by the DOCSIS bridge.