Ethernet Lane Mapping With Continuous Alignment Markers After FEC
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Solution Overview
Problem
Current Ethernet architectures are limited in flexibility and cannot adapt to higher bandwidths beyond 100 G, leading to issues such as misalignment of alignment markers (AMs) and incorrect decoding due to the introduction of Forward Error Correction (FEC), especially at 400 G rates, where the transmission bandwidth of serializer/deserializer (SerDes) is not matched and AMs become disorganized.
Innovation Solution
A data processing method that inserts multiple alignment markers into a transcoded and scrambled data stream, adaptively allocates them to physical coding sublayer (PCS) lanes, performs FEC encoding, and delivers the data to physical medium attachment (PMA) lanes with bit width conversion and idle data insertion to maintain continuous AMs, ensuring correct decoding at higher bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC encoding is introduced to Ethernet architecture, then error correction capability is improved, but alignment markers become disorganized and cannot be correctly identified
Solution Approach 1:
The patent segments the data stream processing by separating alignment marker handling from regular data encoding. Multiple alignment markers are inserted at specific intervals in the data stream, and the FEC encoding is applied selectively to data portions while preserving the integrity and detectability of alignment markers. This segmentation allows the receive end to correctly identify alignment markers even after FEC encoding is applied to the data.
2Productivity
If Ethernet interface bandwidth is increased beyond 100 G, then transmission capacity is improved, but SerDes bandwidth mismatch occurs and AMs cannot be aligned
Solution Approach 1:
The patent introduces dynamic adaptability to the Ethernet architecture by making the alignment marker insertion and lane allocation flexible rather than fixed. The system can dynamically adjust the number and position of alignment markers, and dynamically allocate data to different physical coding sublayer lanes based on the specific bandwidth requirements (100G, 400G, or higher). This dynamic approach allows the same architecture to adapt to different SerDes bandwidths without requiring precise pre-matching.
Solution Approach 2:
The patent changes key parameters of the Ethernet architecture to support higher bandwidths. Specifically, it modifies the alignment marker insertion rate, the number of parallel lanes, and the data allocation strategy according to the target bandwidth. For example, at 400G, the system uses more lanes and adjusts the alignment marker frequency accordingly, allowing the architecture to scale beyond 100G while maintaining proper alignment marker functionality.
3Productivity
If data is allocated to multiple PCS lanes, then transmission bandwidth is improved, but alignment markers become disorganized across lanes
Solution Approach 1:
The patent uses alignment markers as intermediary reference signals that mediate between the data allocation across multiple lanes and the receive end's ability to reconstruct the original data stream. These markers are inserted at calculated positions in each lane based on the allocation pattern, serving as synchronization references that allow the receive end to correctly remap data from multiple lanes back to the original sequence, thereby maintaining alignment marker organization despite parallel transmission.
Data Source
AI summary
A data processing method includes: inserting multiple alignment markers (AMs) into a first data stream, where the first data stream is a data stream that is transcoded and scrambled after being encoded at a physical layer; adaptively allocating the first data stream that includes the multiple AMs to multiple physical coding sublayer (PCS) lanes to obtain second data streams; performing forward error correction (FEC) encoding on the second data streams on the multiple PCS lanes to obtain third data streams; and delivering the third data streams to multiple physical medium attachment (PMA) sublayer lanes according to an input bit width of a serializer/deserializer (SerDes) to obtain multiple fourth data streams, each fourth data stream includes at least one complete and continuous AM, and the at least one AM is an AM in the multiple AMs.