Ethernet PCS Lane Mapping With Alignment Markers After FEC
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Solution Overview
Problem
Existing Ethernet architectures are inflexible and cannot be easily adapted to higher bandwidths beyond 100 G, leading to issues such as misalignment of alignment markers (AMs) and incorrect decoding due to disorganized AMs when forward error correction (FEC) is introduced, especially in scenarios like 400 G transmission.
Innovation Solution
A data processing method that inserts alignment markers into a transcoded and scrambled data stream, adaptively allocates this stream to multiple physical coding sublayer (PCS) lanes, performs FEC encoding, and delivers the data to physical medium attachment sublayer (PMA) lanes to ensure continuous and complete AMs, enabling correct decoding at the receive end.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC encoding is introduced to correct errors in high bandwidth transmission, then transmission reliability is improved, but alignment markers become disorganized and cannot be correctly identified
Solution Approach 1:
The patent segments the data stream into multiple lanes (e.g., 16 lanes for 400G transmission) and inserts alignment markers at specific intervals in each lane. This segmentation allows the receive end to independently process and identify alignment markers from each lane, preventing the disorganization caused by FEC encoding across the entire stream.
Solution Approach 2:
The patent introduces a dedicated alignment marker insertion mechanism that acts as an intermediary between the data source and FEC encoding. These markers serve as reference points that preserve lane identity and alignment information, enabling the receive end to correctly interpret FEC-encoded data by using the markers as anchors for synchronization.
2Ease of manufacture
If Ethernet architecture is designed for 100 G bandwidth with simple structure, then ease of manufacture is improved, but adaptability to higher bandwidths beyond 100 G deteriorates
Solution Approach 1:
The patent designs a universal Ethernet PCS layer architecture that can operate at multiple bandwidths (100G, 200G, 400G, and beyond) by configuring the number of lanes and adjusting the alignment marker insertion intervals. The same basic structure with 64b/66b encoding, scrambling, and alignment marker insertion can be adapted to different bandwidths by changing operational parameters rather than redesigning the entire system.
Solution Approach 2:
The patent introduces dynamic configurability to the Ethernet architecture, allowing the system to adapt to different bandwidth requirements by adjusting the number of active lanes and the frequency of alignment marker insertion. This dynamic approach enables a single architecture to serve multiple bandwidth scenarios without requiring separate fixed designs for each bandwidth level.
3Productivity
If data stream transmission rate is increased beyond 100 G to achieve higher bandwidth, then productivity is improved, but alignment marker continuity and completeness deteriorate
Solution Approach 1:
The patent implements periodic insertion of alignment markers at calculated intervals based on the transmission rate and lane configuration. For higher bandwidths, the system adjusts the periodicity and density of marker insertion to ensure that markers remain detectable and complete despite the increased data rate. This periodic reinforcement of alignment information maintains continuity even as transmission speed increases.
Data Source
Figure 1~2-a
Figure 2-b~3
Figure 4-a~4-b
AI summary
Disclosed are a data processing method, a data transmit end, and a data receive end. The data processing method includes: inserting multiple AMs into a first data stream, where the first data stream is a data stream that is transcoded and scrambled after being encoded at a physical layer, and a transmission rate of the first data stream is greater than or equal to 100 GPS; adaptively allocating the first data stream that includes the AMs to multiple physical coding sublayer PCS lanes to obtain second data streams; performing FEC encoding on the second data streams on the multiple PCS lanes to obtain third data streams; and delivering the third data streams to multiple physical medium attachment sublayer PMA lanes according to an input bit width of a serializer/deserializer Serdes to obtain multiple fourth data streams, where the multiple fourth data streams are in a one-to-one correspondence with the multiple PMA lanes, each fourth data stream includes at least one complete and continuous AM, and the at least one AM is an AM in the multiple AMs.