Ethernet Clock Synchronization via MAC Frame Timestamps

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Solution Overview

Problem

Existing time synchronization methods for independent clocks in tactical radio communication equipment face challenges due to the need for dedicated synchronization signals and complex protocols, particularly in systems with low computing capacity and memory resources, and they often result in clock synchronization inaccuracies and increased complexity.

Innovation Solution

A method and system for time synchronization using standard Ethernet MAC frame packets over a wired Ethernet link, which determines transmission duration and time drift between devices, allowing for clock synchronization without dedicated synchronization wires and reducing complexity by leveraging the Ethernet MAC layer clock directly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If dedicated synchronization wires and specific circuits are used, then clock synchronization accuracy is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the clock synchronization function with the existing Ethernet data transmission function. The same Ethernet wires that carry data packets are also used to transmit timing information embedded within those packets. This eliminates the need for separate synchronization wires and dedicated synchronization circuits, reducing device complexity while maintaining synchronization accuracy through the use of timestamp fields in Ethernet packets.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The Ethernet link is given multi-functionality by using it for both data transmission and clock synchronization. The timing information is embedded within standard Ethernet packets that are already being transmitted for data communication. This universal approach allows the same infrastructure to serve dual purposes, avoiding additional hardware complexity while achieving precise synchronization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If IEEE 1588 standard is implemented for precise clock synchronization, then synchronization accuracy is improved, but implementation complexity increases due to master clock selection process

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidimplementation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the essential timing synchronization function from the complex IEEE 1588 protocol suite. Instead of implementing the full master clock selection and election process, the patent uses a simplified approach where timing information is directly embedded in Ethernet packets and processed locally. This extraction of the core timing function eliminates the complexity of master clock management while preserving synchronization accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Each device independently processes timing information from received Ethernet packets without requiring complex inter-device negotiation or master clock election. The devices self-adjust their clocks based on timestamps embedded in packets, performing synchronization autonomously without the overhead of IEEE 1588's master-slave coordination protocol.

Inventive Principle:
Principle #25Self-service

3Device complexity

If standard Ethernet MAC frame packets are used for synchronization, then device complexity is reduced, but synchronization accuracy may be affected by packet transmission latency variations

Engineering Contradiction:
Improvedevice complexityVSAvoidsynchronization accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where devices exchange timestamp information embedded in Ethernet packets and use these timestamps to calculate and correct timing drift. By continuously monitoring the arrival times of packets with embedded transmission timestamps, devices can adjust their clocks to compensate for latency variations, maintaining synchronization accuracy despite using standard Ethernet packets.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2866365B1Method and system for time synchronization between two device connected by an Ethernet link
Publication Date: 2019.07.17 THALES SA
  • EP2866365B1 patent drawingFigure 1~2
  • EP2866365B1 patent drawingFigure 3a~4a
  • EP2866365B1 patent drawingFigure 3b

AI summary

A method and system for time synchronization between two devices connected by a wired Ethernet link and equipped with a clock. The method comprises the following steps: a step of determining the time required to transmit a data packet between the two devices; a step of transmission by one of the devices of a data packet containing a transmission time; and a step of determining the time by the other device by adding the transmission time to the packet's transmission time. These steps utilize standard Ethernet MAC frame packets.